drm/amdgpu: Set vmid0 PAGE_TABLE_DEPTH for GFX12.1

GFX12.1 uses 2 level gart table. Set the context register appropriately

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
index 7e917eb47a8c118cd8588c386ef0b5114f0698d5..a72770e3d0e997d354db9507c82333c2859ab3da 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
@@ -395,7 +395,10 @@ static void mmhub_v4_2_0_mid_enable_system_domain(struct amdgpu_device *adev,
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
                                    ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
-                                   PAGE_TABLE_DEPTH, 0);
+                                   PAGE_TABLE_DEPTH, adev->gmc.vmid0_page_table_depth);
+               tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
+                                   PAGE_TABLE_BLOCK_SIZE,
+                                   adev->gmc.vmid0_page_table_block_size);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
                                    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
                WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),