static int gfx_v12_1_gfxhub_enable(struct amdgpu_device *adev)
{
- int r;
+ int r, i;
bool value;
r = adev->gfxhub.funcs->gart_enable(adev);
adev->gfxhub.funcs->set_fault_enable_default(adev, value);
/* TODO investigate why TLB flush is needed,
* are we missing a flush somewhere else? */
- adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
+ for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
+ if (AMDGPU_IS_GFXHUB(i))
+ adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(i), 0);
+ }
return 0;
}
value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;
adev->mmhub.funcs->set_fault_enable_default(adev, value);
- gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
+ adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
(unsigned)(adev->gmc.gart_size >> 20),