vassert(0 == (hwcaps_host
& ~(VEX_HWCAPS_AMD64_SSE3
| VEX_HWCAPS_AMD64_CX16
- | VEX_HWCAPS_AMD64_LZCNT)));
+ | VEX_HWCAPS_AMD64_LZCNT
+ | VEX_HWCAPS_AMD64_AVX)));
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
/* SSE3 and CX16 are orthogonal and > baseline, although we really
don't expect to come across anything which can do SSE3 but can't
do CX16. Still, we can handle that case. LZCNT is similarly
- orthogonal. */
+ orthogonal. AVX is technically orthogonal, but just add the
+ cases we actually come across. (This scheme for printing is
+ very stupid. We should add strings independently based on
+ feature bits, but then it would be hard to return a string that
+ didn't need deallocating by the caller.) */
switch (hwcaps) {
case 0:
return "amd64-sse2";
case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
| VEX_HWCAPS_AMD64_LZCNT:
return "amd64-sse3-cx16-lzcnt";
-
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_AVX:
+ return "amd64-sse3-cx16-avx";
default:
return NULL;
}
#define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */
#define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */
#define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */
+#define VEX_HWCAPS_AMD64_AVX (1<<8) /* AVX instructions */
/* ppc32: baseline capability is integer only */
#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */