drm/amd/display: DPCD for Selective Update

[Why&How]
Add flow to read selective update related info from DPCD,
and pass the info to DMUB.

Reviewed-by: Robin Chen <robin.chen@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Jack Chang <jack.chang@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 273610d85438b4c0daa41d57f0df9354168c1826..d0d9297ccac077b0882fbd1fe4996e3fd8829625 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -1167,6 +1167,25 @@ union dpcd_panel_replay_capability_supported {
        unsigned char raw;
 };
 
+union dpcd_panel_replay_capability {
+       struct {
+               unsigned char RESERVED                                                          :2;
+               unsigned char DSC_DECODE_NOT_SUPPORTED                          :1;
+               unsigned char ASYNC_VIDEO_TIMING_NOT_SUPPORTED          :1;
+               unsigned char DSC_CRC_OF_MULTI_SU_SUPPORTED                     :1;
+               unsigned char PR_SU_GRANULARITY_NEEDED                          :1;
+               unsigned char SU_Y_GRANULARITY_EXT_CAP_SUPPORTED        :1;
+               unsigned char LINK_OFF_SUPPORTED_IN_PR_ACTIVE           :1;
+       } bits;
+       unsigned char raw;
+};
+
+struct dpcd_panel_replay_selective_update_info {
+       uint16_t pr_su_x_granularity;
+       uint8_t pr_su_y_granularity;
+       uint16_t pr_su_y_granularity_extended_caps;
+};
+
 enum dpcd_downstream_port_max_bpc {
        DOWN_STREAM_MAX_8BPC = 0,
        DOWN_STREAM_MAX_10BPC,
@@ -1290,7 +1309,9 @@ struct dpcd_caps {
        struct edp_psr_info psr_info;
 
        struct replay_info pr_info;
-       union dpcd_panel_replay_capability_supported pr_caps_supported;
+       union dpcd_panel_replay_capability_supported vesa_replay_caps_supported;
+       union dpcd_panel_replay_capability vesa_replay_caps;
+       struct dpcd_panel_replay_selective_update_info vesa_replay_su_info;
        uint16_t edp_oled_emission_rate;
        union dp_receive_port0_cap receive_port0_cap;
        /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 54c417928b61a303f5e89cdf069b6125b8e5054c..8bbf5637b166b7c187b76b87e7efaaab0235152b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -1593,6 +1593,41 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
        return true;
 }
 
+static void retrieve_vesa_replay_su_info(struct dc_link *link)
+{
+       uint8_t dpcd_data = 0;
+
+       core_link_read_dpcd(link,
+               DP_PR_SU_X_GRANULARITY_LOW,
+               &dpcd_data,
+               sizeof(dpcd_data));
+       link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity = dpcd_data;
+
+       core_link_read_dpcd(link,
+               DP_PR_SU_X_GRANULARITY_HIGH,
+               &dpcd_data,
+               sizeof(dpcd_data));
+       link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity |= (dpcd_data << 8);
+
+       core_link_read_dpcd(link,
+               DP_PR_SU_Y_GRANULARITY,
+               &dpcd_data,
+               sizeof(dpcd_data));
+       link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity = dpcd_data;
+
+       core_link_read_dpcd(link,
+               DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW,
+               &dpcd_data,
+               sizeof(dpcd_data));
+       link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps = dpcd_data;
+
+       core_link_read_dpcd(link,
+               DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH,
+               &dpcd_data,
+               sizeof(dpcd_data));
+       link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps |= (dpcd_data << 8);
+}
+
 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
 {
        uint8_t lttpr_dpcd_data[10] = {0};
@@ -2094,8 +2129,16 @@ static bool retrieve_link_cap(struct dc_link *link)
 
        core_link_read_dpcd(link,
                        DP_PANEL_REPLAY_CAPABILITY_SUPPORT,
-                       &link->dpcd_caps.pr_caps_supported.raw,
-                       sizeof(link->dpcd_caps.pr_caps_supported.raw));
+                       &link->dpcd_caps.vesa_replay_caps_supported.raw,
+                       sizeof(link->dpcd_caps.vesa_replay_caps_supported.raw));
+
+       core_link_read_dpcd(link,
+                       DP_PANEL_REPLAY_CAPABILITY,
+                       &link->dpcd_caps.vesa_replay_caps.raw,
+                       sizeof(link->dpcd_caps.vesa_replay_caps.raw));
+
+       /* Read VESA Panel Replay Selective Update caps */
+       retrieve_vesa_replay_su_info(link);
 
        /* Read DP tunneling information. */
        status = dpcd_get_tunneling_device_data(link);

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 3168c42d662cd26efcb750c15eb8644d50e9d242..fdbfa5103183b8375efc8d4516f62a73386684e1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -113,7 +113,10 @@ static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_s
                pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1;
 
                pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0;
-               pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 0;
+
+               if (link->dpcd_caps.vesa_replay_caps.bits.SU_Y_GRANULARITY_EXT_CAP_SUPPORTED)
+                       pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 1;
+
                pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0;
 
                dm_helpers_dp_write_dpcd(link->ctx, link,
@@ -231,6 +234,17 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
        cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
        cmd.pr_copy_settings.data.debug.u32All = link->replay_settings.config.debug_flags;
 
+       cmd.pr_copy_settings.data.su_granularity_needed = link->dpcd_caps.vesa_replay_caps.bits.PR_SU_GRANULARITY_NEEDED;
+       cmd.pr_copy_settings.data.su_x_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity;
+       cmd.pr_copy_settings.data.su_y_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity;
+       cmd.pr_copy_settings.data.su_y_granularity_extended_caps =
+               link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps;
+
+       if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0)
+               cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable +
+                       pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /
+                       pipe_ctx->stream->timing.dsc_cfg.num_slices_v;
+
        dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
index 8445c540f042c4a29674a2594a00e79475f4b436..43d58df67babafc2aadc6925044581804809e2d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
@@ -37,6 +37,21 @@
 #ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h
 #define DP_PANEL_REPLAY_CAPABILITY 0x0b1
 #endif /* DP_PANEL_REPLAY_CAPABILITY */
+#ifndef DP_PR_SU_X_GRANULARITY_LOW         // can remove this once the define gets into linux drm_dp_helper.h
+#define DP_PR_SU_X_GRANULARITY_LOW                     0x0b2
+#endif /* DP_PR_SU_X_GRANULARITY_LOW */
+#ifndef DP_PR_SU_X_GRANULARITY_HIGH        // can remove this once the define gets into linux drm_dp_helper.h
+#define DP_PR_SU_X_GRANULARITY_HIGH                    0x0b3
+#endif /* DP_PR_SU_X_GRANULARITY_HIGH */
+#ifndef DP_PR_SU_Y_GRANULARITY             // can remove this once the define gets into linux drm_dp_helper.h
+#define DP_PR_SU_Y_GRANULARITY                         0x0b4
+#endif /* DP_PR_SU_Y_GRANULARITY */
+#ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW // can remove this once the define gets into linux drm_dp_helper.h
+#define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW                0x0b5
+#endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW */
+#ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH // can remove this once the define gets into linux drm_dp_helper.h
+#define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH       0x0b6
+#endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH */
 #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  // can remove this once the define gets into linux drm_dp_helper.h
 #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  0x1b0
 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */