#include "libvex_guest_ppc64.h"
+/* The PPC64 register layout with vs register support (Power 7 and beyond)
+ consists of 64 VSR registers of size 128-bits. The 32 floating point
+ registers fp map to the upper 64-bits of vsr[0] to vsr[31]. The 32
+ vr[0] to vr[31] registers of size 128-bits map to vsr[31] to vsr[63]. The
+ lower 64-bits of the vsr[0] to vsr[31] registers are in the pseudo
+ registers vs[0]h to vs[31]h registers. These pseudo registers get printed
+ by GDB but there are no instructions that directly access these registers.
+ When GDB prints the vsr[0] to vsr[31] registers it combines the contents
+ of the floating point registers fp[0] to fp[31] and its corresponding
+ vs[0]h to vs[31]h registers to display the VSR contents. The vsr[32]
+ to vsr[63] contents are the same as the the vr[0] to vr[31] contents.
+
+ GDB also prints fp[32] to fp[63]. These are simply the upper 64 bits of
+ vsr[32] to vsr[63] however, these are not "real" floating point registers
+ as none of the floating point instructions can access these registers.
+
+ Register map.
+ MSB IBM bit numbering LSB
+ 0 63 64 127
+ vsr[0] | fp[0] | vs[0]h |
+ vsr[1] | fp[1] | vs[1]h |
+ vsr[2] | fp[2] | vs[2]h |
+ ...
+ vsr[31] | fp[31] | vs[31]h |
+ vsr[32] | vr[0] |
+ vsr[33] | vr[1] |
+ ...
+ vsr[63] | vr[31] |
+
+ Note, not shown above are the fake fp[32] to fp[63] that GDB prints
+
+ Valgrind has two shadow registers for each real register denoted with
+ the suffix s1 and s2. When printing the contents of the shadow registers,
+ GDB does not explicitly print the shadow registers vsr[0] to vsr[63]. GDB
+ prints the shadow register contents of the 32 floating point registers as
+ fp[0]s1 to fp[31]s1 and fp[0]s2 to fp[31]s2. The shadow register contents
+ of vs[0]hs1 to vs[31]hs1 and vs[0]hs2 to vs[31]hs2 are also printed. The
+ user needs to construct the vsr[i]s1 shadow register contents by looking
+ at fp[i]s1 for the upper 64-bits and vs[i]hs1 for the lower 64-bits. The
+ vsr[i]s2 shadow register contents are constructed similarly.
+
+ GDB prints the 128-bit shadow register contents of the 32 vr registers as
+ vr[0]s1 to vr[31]s1 and vr[0]s2 to vr[31]s2. These are also the value of the
+ VSR shadow registers vsr[32]s1 to vsr[63]s1 and vsr[32]s2 to vsr[63]s2. */
+
static struct reg regs[] = {
{ "r0", 0, 64 },
{ "r1", 64, 64 },
{ "vr31", 8544, 128 },
{ "vscr", 8672, 32 },
{ "vrsave", 8704, 32 },
+ { "vs0h", 8736, 64 },
+ { "vs1h", 8800, 64 },
+ { "vs2h", 8864, 64 },
+ { "vs3h", 8928, 64 },
+ { "vs4h", 8992, 64 },
+ { "vs5h", 9056, 64 },
+ { "vs6h", 9120, 64 },
+ { "vs7h", 9184, 64 },
+ { "vs8h", 9248, 64 },
+ { "vs9h", 9312, 64 },
+ { "vs10h", 9376, 64 },
+ { "vs11h", 9440, 64 },
+ { "vs12h", 9504, 64 },
+ { "vs13h", 9568, 64 },
+ { "vs14h", 9632, 64 },
+ { "vs15h", 9696, 64 },
+ { "vs16h", 9760, 64 },
+ { "vs17h", 9824, 64 },
+ { "vs18h", 9888, 64 },
+ { "vs19h", 9952, 64 },
+ { "vs20h", 10016, 64 },
+ { "vs21h", 10080, 64 },
+ { "vs22h", 10144, 64 },
+ { "vs23h", 10208, 64 },
+ { "vs24h", 10272, 64 },
+ { "vs25h", 10336, 64 },
+ { "vs26h", 10400, 64 },
+ { "vs27h", 10464, 64 },
+ { "vs28h", 10528, 64 },
+ { "vs29h", 10592, 64 },
+ { "vs30h", 10656, 64 },
+ { "vs31h", 10720, 64 },
};
+
static const char *expedite_regs[] = { "r1", "pc", 0 };
#define num_regs (sizeof (regs) / sizeof (regs[0]))
ThreadState* tst = VG_(get_ThreadState)(tid);
int set = abs_regno / num_regs;
int regno = abs_regno % num_regs;
+ int low_offset, high_offset;
+
*mod = False;
VexGuestPPC64State* ppc64 = (VexGuestPPC64State*) get_arch (set, tst);
- switch (regno) {
+
+#if defined (VG_LITTLEENDIAN)
+ /* Fetch the 64-bits for the VR registers (VSR[32] to VSR[63] stored as
+ * Little Endian. The 128-bit value is stored as an array of four 32-bit
+ * values. The lower 32-bits are in element 0 in Little Endian format.
+ */
+ low_offset = 0;
+
+ /* Fetch the upper 64-bits for the floating point register stored as
+ * Little Endian. The 128-bit value is stored as an array of four 32-bit
+ * values. The upper 32-bits are in element 3 in Little Endian format.
+ */
+ high_offset = 2;
+#elif defined (VG_BIGENDIAN)
+ /* Fetch the 64-bits for the VR registers (VSR[32] to VSR[63] stored as
+ * Little Endian. The 128-bit value is stored as an array of four 32-bit
+ * values. The lower 32-bits are in element 3 in Big Endian format.
+ */
+ low_offset = 2;
+
+ /* Fetch the upper 64-bits for the floating point register stored as
+ * Little Endian. The 128-bit value is stored as an array of four 32-bit
+ * values. The upper 32-bits are in element 0 in Big Endian format.
+ */
+ high_offset = 0;
+#else
+# error "Unknown endianness"
+#endif
+
+ switch (regno) {
// numbers here have to match the order of regs above
// Attention: gdb order does not match valgrind order.
case 0: VG_(transfer) (&ppc64->guest_GPR0, buf, dir, size, mod); break;
case 29: VG_(transfer) (&ppc64->guest_GPR29, buf, dir, size, mod); break;
case 30: VG_(transfer) (&ppc64->guest_GPR30, buf, dir, size, mod); break;
case 31: VG_(transfer) (&ppc64->guest_GPR31, buf, dir, size, mod); break;
- case 32: VG_(transfer) (&ppc64->guest_VSR0, buf, dir, size, mod); break;
- case 33: VG_(transfer) (&ppc64->guest_VSR1, buf, dir, size, mod); break;
- case 34: VG_(transfer) (&ppc64->guest_VSR2, buf, dir, size, mod); break;
- case 35: VG_(transfer) (&ppc64->guest_VSR3, buf, dir, size, mod); break;
- case 36: VG_(transfer) (&ppc64->guest_VSR4, buf, dir, size, mod); break;
- case 37: VG_(transfer) (&ppc64->guest_VSR5, buf, dir, size, mod); break;
- case 38: VG_(transfer) (&ppc64->guest_VSR6, buf, dir, size, mod); break;
- case 39: VG_(transfer) (&ppc64->guest_VSR7, buf, dir, size, mod); break;
- case 40: VG_(transfer) (&ppc64->guest_VSR8, buf, dir, size, mod); break;
- case 41: VG_(transfer) (&ppc64->guest_VSR9, buf, dir, size, mod); break;
- case 42: VG_(transfer) (&ppc64->guest_VSR10, buf, dir, size, mod); break;
- case 43: VG_(transfer) (&ppc64->guest_VSR11, buf, dir, size, mod); break;
- case 44: VG_(transfer) (&ppc64->guest_VSR12, buf, dir, size, mod); break;
- case 45: VG_(transfer) (&ppc64->guest_VSR13, buf, dir, size, mod); break;
- case 46: VG_(transfer) (&ppc64->guest_VSR14, buf, dir, size, mod); break;
- case 47: VG_(transfer) (&ppc64->guest_VSR15, buf, dir, size, mod); break;
- case 48: VG_(transfer) (&ppc64->guest_VSR16, buf, dir, size, mod); break;
- case 49: VG_(transfer) (&ppc64->guest_VSR17, buf, dir, size, mod); break;
- case 50: VG_(transfer) (&ppc64->guest_VSR18, buf, dir, size, mod); break;
- case 51: VG_(transfer) (&ppc64->guest_VSR19, buf, dir, size, mod); break;
- case 52: VG_(transfer) (&ppc64->guest_VSR20, buf, dir, size, mod); break;
- case 53: VG_(transfer) (&ppc64->guest_VSR21, buf, dir, size, mod); break;
- case 54: VG_(transfer) (&ppc64->guest_VSR22, buf, dir, size, mod); break;
- case 55: VG_(transfer) (&ppc64->guest_VSR23, buf, dir, size, mod); break;
- case 56: VG_(transfer) (&ppc64->guest_VSR24, buf, dir, size, mod); break;
- case 57: VG_(transfer) (&ppc64->guest_VSR25, buf, dir, size, mod); break;
- case 58: VG_(transfer) (&ppc64->guest_VSR26, buf, dir, size, mod); break;
- case 59: VG_(transfer) (&ppc64->guest_VSR27, buf, dir, size, mod); break;
- case 60: VG_(transfer) (&ppc64->guest_VSR28, buf, dir, size, mod); break;
- case 61: VG_(transfer) (&ppc64->guest_VSR29, buf, dir, size, mod); break;
- case 62: VG_(transfer) (&ppc64->guest_VSR30, buf, dir, size, mod); break;
- case 63: VG_(transfer) (&ppc64->guest_VSR31, buf, dir, size, mod); break;
+
+ case 32: VG_(transfer) (&ppc64->guest_VSR0[high_offset], buf, dir, size, mod); break;
+ case 33: VG_(transfer) (&ppc64->guest_VSR1[high_offset], buf, dir, size, mod); break;
+ case 34: VG_(transfer) (&ppc64->guest_VSR2[high_offset], buf, dir, size, mod); break;
+ case 35: VG_(transfer) (&ppc64->guest_VSR3[high_offset], buf, dir, size, mod); break;
+ case 36: VG_(transfer) (&ppc64->guest_VSR4[high_offset], buf, dir, size, mod); break;
+ case 37: VG_(transfer) (&ppc64->guest_VSR5[high_offset], buf, dir, size, mod); break;
+ case 38: VG_(transfer) (&ppc64->guest_VSR6[high_offset], buf, dir, size, mod); break;
+ case 39: VG_(transfer) (&ppc64->guest_VSR7[high_offset], buf, dir, size, mod); break;
+ case 40: VG_(transfer) (&ppc64->guest_VSR8[high_offset], buf, dir, size, mod); break;
+ case 41: VG_(transfer) (&ppc64->guest_VSR9[high_offset], buf, dir, size, mod); break;
+ case 42: VG_(transfer) (&ppc64->guest_VSR10[high_offset], buf, dir, size, mod); break;
+ case 43: VG_(transfer) (&ppc64->guest_VSR11[high_offset], buf, dir, size, mod); break;
+ case 44: VG_(transfer) (&ppc64->guest_VSR12[high_offset], buf, dir, size, mod); break;
+ case 45: VG_(transfer) (&ppc64->guest_VSR13[high_offset], buf, dir, size, mod); break;
+ case 46: VG_(transfer) (&ppc64->guest_VSR14[high_offset], buf, dir, size, mod); break;
+ case 47: VG_(transfer) (&ppc64->guest_VSR15[high_offset], buf, dir, size, mod); break;
+ case 48: VG_(transfer) (&ppc64->guest_VSR16[high_offset], buf, dir, size, mod); break;
+ case 49: VG_(transfer) (&ppc64->guest_VSR17[high_offset], buf, dir, size, mod); break;
+ case 50: VG_(transfer) (&ppc64->guest_VSR18[high_offset], buf, dir, size, mod); break;
+ case 51: VG_(transfer) (&ppc64->guest_VSR19[high_offset], buf, dir, size, mod); break;
+ case 52: VG_(transfer) (&ppc64->guest_VSR20[high_offset], buf, dir, size, mod); break;
+ case 53: VG_(transfer) (&ppc64->guest_VSR21[high_offset], buf, dir, size, mod); break;
+ case 54: VG_(transfer) (&ppc64->guest_VSR22[high_offset], buf, dir, size, mod); break;
+ case 55: VG_(transfer) (&ppc64->guest_VSR23[high_offset], buf, dir, size, mod); break;
+ case 56: VG_(transfer) (&ppc64->guest_VSR24[high_offset], buf, dir, size, mod); break;
+ case 57: VG_(transfer) (&ppc64->guest_VSR25[high_offset], buf, dir, size, mod); break;
+ case 58: VG_(transfer) (&ppc64->guest_VSR26[high_offset], buf, dir, size, mod); break;
+ case 59: VG_(transfer) (&ppc64->guest_VSR27[high_offset], buf, dir, size, mod); break;
+ case 60: VG_(transfer) (&ppc64->guest_VSR28[high_offset], buf, dir, size, mod); break;
+ case 61: VG_(transfer) (&ppc64->guest_VSR29[high_offset], buf, dir, size, mod); break;
+ case 62: VG_(transfer) (&ppc64->guest_VSR30[high_offset], buf, dir, size, mod); break;
+ case 63: VG_(transfer) (&ppc64->guest_VSR31[high_offset], buf, dir, size, mod); break;
+
case 64: VG_(transfer) (&ppc64->guest_CIA, buf, dir, size, mod); break;
case 65: *mod = False; break; // VEX does not model Machine State Register
case 66: {
UInt cr = LibVEX_GuestPPC64_get_CR (ppc64);
if (dir == valgrind_to_gdbserver) {
- VG_(transfer) (&cr, buf, dir, size, mod);
+ VG_(transfer) (&cr, buf, dir, size, mod);
} else {
UInt newcr;
VG_(transfer) (&newcr, buf, dir, size, mod);
case 70: VG_(transfer) (&ppc64->guest_FPROUND, buf, dir, size, mod); break;
case 71: *mod = False; break; // GDBTD???? VEX { "orig_r3", 4448, 64 },
case 72: *mod = False; break; // GDBTD???? VEX { "trap", 4512, 64 },
- case 73: VG_(transfer) (&ppc64->guest_VSR32, buf, dir, size, mod); break;
- case 74: VG_(transfer) (&ppc64->guest_VSR33, buf, dir, size, mod); break;
- case 75: VG_(transfer) (&ppc64->guest_VSR34, buf, dir, size, mod); break;
- case 76: VG_(transfer) (&ppc64->guest_VSR35, buf, dir, size, mod); break;
- case 77: VG_(transfer) (&ppc64->guest_VSR36, buf, dir, size, mod); break;
- case 78: VG_(transfer) (&ppc64->guest_VSR37, buf, dir, size, mod); break;
- case 79: VG_(transfer) (&ppc64->guest_VSR38, buf, dir, size, mod); break;
- case 80: VG_(transfer) (&ppc64->guest_VSR39, buf, dir, size, mod); break;
- case 81: VG_(transfer) (&ppc64->guest_VSR40, buf, dir, size, mod); break;
- case 82: VG_(transfer) (&ppc64->guest_VSR41, buf, dir, size, mod); break;
- case 83: VG_(transfer) (&ppc64->guest_VSR42, buf, dir, size, mod); break;
- case 84: VG_(transfer) (&ppc64->guest_VSR43, buf, dir, size, mod); break;
- case 85: VG_(transfer) (&ppc64->guest_VSR44, buf, dir, size, mod); break;
- case 86: VG_(transfer) (&ppc64->guest_VSR45, buf, dir, size, mod); break;
- case 87: VG_(transfer) (&ppc64->guest_VSR46, buf, dir, size, mod); break;
- case 88: VG_(transfer) (&ppc64->guest_VSR47, buf, dir, size, mod); break;
- case 89: VG_(transfer) (&ppc64->guest_VSR48, buf, dir, size, mod); break;
- case 90: VG_(transfer) (&ppc64->guest_VSR49, buf, dir, size, mod); break;
- case 91: VG_(transfer) (&ppc64->guest_VSR50, buf, dir, size, mod); break;
- case 92: VG_(transfer) (&ppc64->guest_VSR51, buf, dir, size, mod); break;
- case 93: VG_(transfer) (&ppc64->guest_VSR52, buf, dir, size, mod); break;
- case 94: VG_(transfer) (&ppc64->guest_VSR53, buf, dir, size, mod); break;
- case 95: VG_(transfer) (&ppc64->guest_VSR54, buf, dir, size, mod); break;
- case 96: VG_(transfer) (&ppc64->guest_VSR55, buf, dir, size, mod); break;
- case 97: VG_(transfer) (&ppc64->guest_VSR56, buf, dir, size, mod); break;
- case 98: VG_(transfer) (&ppc64->guest_VSR57, buf, dir, size, mod); break;
- case 99: VG_(transfer) (&ppc64->guest_VSR58, buf, dir, size, mod); break;
- case 100: VG_(transfer) (&ppc64->guest_VSR59, buf, dir, size, mod); break;
- case 101: VG_(transfer) (&ppc64->guest_VSR60, buf, dir, size, mod); break;
- case 102: VG_(transfer) (&ppc64->guest_VSR61, buf, dir, size, mod); break;
- case 103: VG_(transfer) (&ppc64->guest_VSR62, buf, dir, size, mod); break;
- case 104: VG_(transfer) (&ppc64->guest_VSR63, buf, dir, size, mod); break;
- case 105: VG_(transfer) (&ppc64->guest_VSCR, buf, dir, size, mod); break;
+
+ case 73: VG_(transfer) (&ppc64->guest_VSR32, buf, dir, size, mod); break;
+ case 74: VG_(transfer) (&ppc64->guest_VSR33, buf, dir, size, mod); break;
+ case 75: VG_(transfer) (&ppc64->guest_VSR34, buf, dir, size, mod); break;
+ case 76: VG_(transfer) (&ppc64->guest_VSR35, buf, dir, size, mod); break;
+ case 77: VG_(transfer) (&ppc64->guest_VSR36, buf, dir, size, mod); break;
+ case 78: VG_(transfer) (&ppc64->guest_VSR37, buf, dir, size, mod); break;
+ case 79: VG_(transfer) (&ppc64->guest_VSR38, buf, dir, size, mod); break;
+ case 80: VG_(transfer) (&ppc64->guest_VSR39, buf, dir, size, mod); break;
+ case 81: VG_(transfer) (&ppc64->guest_VSR40, buf, dir, size, mod); break;
+ case 82: VG_(transfer) (&ppc64->guest_VSR40, buf, dir, size, mod); break;
+ case 83: VG_(transfer) (&ppc64->guest_VSR42, buf, dir, size, mod); break;
+ case 84: VG_(transfer) (&ppc64->guest_VSR43, buf, dir, size, mod); break;
+ case 85: VG_(transfer) (&ppc64->guest_VSR44, buf, dir, size, mod); break;
+ case 86: VG_(transfer) (&ppc64->guest_VSR45, buf, dir, size, mod); break;
+ case 87: VG_(transfer) (&ppc64->guest_VSR46, buf, dir, size, mod); break;
+ case 88: VG_(transfer) (&ppc64->guest_VSR47, buf, dir, size, mod); break;
+ case 89: VG_(transfer) (&ppc64->guest_VSR48, buf, dir, size, mod); break;
+ case 90: VG_(transfer) (&ppc64->guest_VSR49, buf, dir, size, mod); break;
+ case 91: VG_(transfer) (&ppc64->guest_VSR50, buf, dir, size, mod); break;
+ case 92: VG_(transfer) (&ppc64->guest_VSR51, buf, dir, size, mod); break;
+ case 93: VG_(transfer) (&ppc64->guest_VSR52, buf, dir, size, mod); break;
+ case 94: VG_(transfer) (&ppc64->guest_VSR53, buf, dir, size, mod); break;
+ case 95: VG_(transfer) (&ppc64->guest_VSR54, buf, dir, size, mod); break;
+ case 96: VG_(transfer) (&ppc64->guest_VSR55, buf, dir, size, mod); break;
+ case 97: VG_(transfer) (&ppc64->guest_VSR56, buf, dir, size, mod); break;
+ case 98: VG_(transfer) (&ppc64->guest_VSR57, buf, dir, size, mod); break;
+ case 99: VG_(transfer) (&ppc64->guest_VSR58, buf, dir, size, mod); break;
+ case 100: VG_(transfer) (&ppc64->guest_VSR59, buf, dir, size, mod); break;
+ case 101: VG_(transfer) (&ppc64->guest_VSR60, buf, dir, size, mod); break;
+ case 102: VG_(transfer) (&ppc64->guest_VSR61, buf, dir, size, mod); break;
+ case 103: VG_(transfer) (&ppc64->guest_VSR62, buf, dir, size, mod); break;
+ case 104: VG_(transfer) (&ppc64->guest_VSR63, buf, dir, size, mod); break;
+ case 105: VG_(transfer) (&ppc64->guest_VSCR, buf, dir, size, mod); break;
case 106: VG_(transfer) (&ppc64->guest_VRSAVE, buf, dir, size, mod); break;
+
+ /* Fetch the lower 64-bits of the VSR registers. GDB will combine the
+ * lower 64-bits of the VSR with the upper 64-bits it got fetching the
+ * corresponding floating point register to display the full 128-bit
+ * VSR value.
+ */
+ case 107: VG_(transfer) (&ppc64->guest_VSR0[low_offset], buf, dir, size, mod); break;
+ case 108: VG_(transfer) (&ppc64->guest_VSR1[low_offset], buf, dir, size, mod); break;
+ case 109: VG_(transfer) (&ppc64->guest_VSR2[low_offset], buf, dir, size, mod); break;
+ case 110: VG_(transfer) (&ppc64->guest_VSR3[low_offset], buf, dir, size, mod); break;
+ case 111: VG_(transfer) (&ppc64->guest_VSR4[low_offset], buf, dir, size, mod); break;
+ case 112: VG_(transfer) (&ppc64->guest_VSR5[low_offset], buf, dir, size, mod); break;
+ case 113: VG_(transfer) (&ppc64->guest_VSR6[low_offset], buf, dir, size, mod); break;
+ case 114: VG_(transfer) (&ppc64->guest_VSR7[low_offset], buf, dir, size, mod); break;
+ case 115: VG_(transfer) (&ppc64->guest_VSR8[low_offset], buf, dir, size, mod); break;
+ case 116: VG_(transfer) (&ppc64->guest_VSR9[low_offset], buf, dir, size, mod); break;
+ case 117: VG_(transfer) (&ppc64->guest_VSR10[low_offset], buf, dir, size, mod); break;
+ case 118: VG_(transfer) (&ppc64->guest_VSR11[low_offset], buf, dir, size, mod); break;
+ case 119: VG_(transfer) (&ppc64->guest_VSR12[low_offset], buf, dir, size, mod); break;
+ case 120: VG_(transfer) (&ppc64->guest_VSR13[low_offset], buf, dir, size, mod); break;
+ case 121: VG_(transfer) (&ppc64->guest_VSR14[low_offset], buf, dir, size, mod); break;
+ case 122: VG_(transfer) (&ppc64->guest_VSR15[low_offset], buf, dir, size, mod); break;
+ case 123: VG_(transfer) (&ppc64->guest_VSR16[low_offset], buf, dir, size, mod); break;
+ case 124: VG_(transfer) (&ppc64->guest_VSR17[low_offset], buf, dir, size, mod); break;
+ case 125: VG_(transfer) (&ppc64->guest_VSR18[low_offset], buf, dir, size, mod); break;
+ case 126: VG_(transfer) (&ppc64->guest_VSR19[low_offset], buf, dir, size, mod); break;
+ case 127: VG_(transfer) (&ppc64->guest_VSR20[low_offset], buf, dir, size, mod); break;
+ case 128: VG_(transfer) (&ppc64->guest_VSR21[low_offset], buf, dir, size, mod); break;
+ case 129: VG_(transfer) (&ppc64->guest_VSR22[low_offset], buf, dir, size, mod); break;
+ case 130: VG_(transfer) (&ppc64->guest_VSR23[low_offset], buf, dir, size, mod); break;
+ case 131: VG_(transfer) (&ppc64->guest_VSR24[low_offset], buf, dir, size, mod); break;
+ case 132: VG_(transfer) (&ppc64->guest_VSR25[low_offset], buf, dir, size, mod); break;
+ case 133: VG_(transfer) (&ppc64->guest_VSR26[low_offset], buf, dir, size, mod); break;
+ case 134: VG_(transfer) (&ppc64->guest_VSR27[low_offset], buf, dir, size, mod); break;
+ case 135: VG_(transfer) (&ppc64->guest_VSR28[low_offset], buf, dir, size, mod); break;
+ case 136: VG_(transfer) (&ppc64->guest_VSR29[low_offset], buf, dir, size, mod); break;
+ case 137: VG_(transfer) (&ppc64->guest_VSR30[low_offset], buf, dir, size, mod); break;
+ case 138: VG_(transfer) (&ppc64->guest_VSR31[low_offset], buf, dir, size, mod); break;
default: vg_assert(0);
}
}
static
const char* target_xml (Bool shadow_mode)
{
+ /* NOTE, the current powerpc-altivec64l*.xml files includes the vsx
+ * registers. Power 6 and earlier power processors do not support the
+ * vsx registers. GDB has a bug in that it is only checking for ptrace
+ * support rather then checking the actual HW feature. Hence GDB on
+ * power 6 prints vsx registers that do not exist. Valgrind GDB support
+ * also has to include the vsx register definitions to be consistent with
+ * GDB.
+ */
if (shadow_mode) {
return "powerpc-altivec64l-valgrind.xml";
} else {
projects / thirdparty / valgrind.git / commitdiff
