target/riscv: Inline translator_ld[uw,l,q]() calls

In preparation of removing the translator_ld[uw,l,q]() methods,
inline them for the RISC-V targets, using mo_endian(ctx) -- which
we introduced in commit 504f7f304ff -- instead of MO_TE.

Mechanical change using the following Coccinelle 'spatch' script:

    @@
    expression env, db, pc, do_swap;
    @@
    (
    - translator_lduw(env, db, pc)
    + translator_lduw_end(env, db, pc, mo_endian(ctx))
    |
    - translator_ldl(env, db, pc)
    + translator_ldl_end(env, db, pc, mo_endian(ctx))
    |
    - translator_ldq(env, db, pc)
    + translator_ldq_end(env, db, pc, mo_endian(ctx))
    )

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260202213810.97141-1-philmd@linaro.org>

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4a2c08243d189149792b709067465f4b45de3ba4..cb4f44360185f62485bbd955c09a0e742f76e447 100644 (file)
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1254,13 +1254,16 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
          * real one is 2 or 4 bytes. Instruction preload wouldn't trigger
          * additional page fault.
          */
-        opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
+        opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,
+                                    mo_endian(ctx));
     } else {
         /*
          * For unaligned pc, instruction preload may trigger additional
          * page fault so we only load 2 bytes here.
          */
-        opcode = (uint32_t) translator_lduw(env, &ctx->base, ctx->base.pc_next);
+        opcode = (uint32_t) translator_lduw_end(env, &ctx->base,
+                                                ctx->base.pc_next,
+                                                mo_endian(ctx));
     }
     ctx->ol = ctx->xl;
 
@@ -1280,8 +1283,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
         if (!pc_is_4byte_align) {
             /* Load last 2 bytes of instruction here */
             opcode = deposit32(opcode, 16, 16,
-                               translator_lduw(env, &ctx->base,
-                                               ctx->base.pc_next + 2));
+                               translator_lduw_end(env, &ctx->base,
+                                                   ctx->base.pc_next + 2,
+                                                   mo_endian(ctx)));
         }
         ctx->opcode = opcode;
 
@@ -1396,7 +1400,8 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 
             if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
                 uint16_t next_insn =
-                    translator_lduw(env, &ctx->base, ctx->base.pc_next);
+                    translator_lduw_end(env, &ctx->base, ctx->base.pc_next,
+                                        mo_endian(ctx));
                 int len = insn_len(next_insn);
 
                 if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {