]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
h8300.c (fix_bit_operand): Don't generate insns by hand.
authorKazu Hirata <kazu@cs.umass.edu>
Tue, 17 Feb 2004 23:44:14 +0000 (23:44 +0000)
committerKazu Hirata <kazu@gcc.gnu.org>
Tue, 17 Feb 2004 23:44:14 +0000 (23:44 +0000)
* config/h8300/h8300.c (fix_bit_operand): Don't generate insns
by hand.
* config/h8300/h8300.md (*andqi3_1): Change to andqi3_1.
(*iorqi3_1): Change to iorqi3_1.
(*xorqi3_1): Change to xorqi3_1.

From-SVN: r77997

gcc/ChangeLog
gcc/config/h8300/h8300.c
gcc/config/h8300/h8300.md

index 3dd2ff8a1be40711700cbdac659c325e17373aa2..42612f040888ae4108d1b472cb27da9c24458a34 100644 (file)
@@ -1,3 +1,11 @@
+2004-02-17  Kazu Hirata  <kazu@cs.umass.edu>
+
+       * config/h8300/h8300.c (fix_bit_operand): Don't generate insns
+       by hand.
+       * config/h8300/h8300.md (*andqi3_1): Change to andqi3_1.
+       (*iorqi3_1): Change to iorqi3_1.
+       (*xorqi3_1): Change to xorqi3_1.
+
 2004-02-17  Kazu Hirata  <kazu@cs.umass.edu>
 
        * c-common.c, cfghooks.c, rtlanal.c, varasm.c: Fix comment
index a06f87ced6eb4ec196701cbdab031df83259cb19..894c3aa3c2bb2d4c14809b4b5baaf22903061a8a 100644 (file)
@@ -4109,10 +4109,21 @@ fix_bit_operand (rtx *operands, int what, enum rtx_code type)
   operands[1] = force_reg (QImode, operands[1]);
   {
     rtx res = gen_reg_rtx (QImode);
-    emit_insn (gen_rtx_SET (VOIDmode, res,
-                           gen_rtx_fmt_ee (type, QImode,
-                                           operands[1], operands[2])));
-    emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
+    switch (type)
+      {
+      case AND:
+       emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
+       break;
+      case IOR:
+       emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
+       break;
+      case XOR:
+       emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
+       break;
+      default:
+       abort ();
+      }
+    emit_insn (gen_movqi (operands[0], res));
   }
   return 1;
 }
index 8671e1f220332ffe55172c0facc12fd09b33383b..f18f007574b59e137dc2903d1d714b28aa5d6399 100644 (file)
 ;; AND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*andqi3_1"
+(define_insn "andqi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
        (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
 ;; OR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*iorqi3_1"
+(define_insn "iorqi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
        (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
 ;; XOR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*xorqi3_1"
+(define_insn "xorqi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
        (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "rn,n")))]