arm64: dts: renesas: r9a08g046: Add GBETH nodes

Renesas RZ/G3L SoC is equipped with 2x Synopsys DesignWare Ethernet
(10/100/1000 BASE) with TSN, IP block version 5.30. Add GBETH nodes
to R9A08G046 RZ/G3L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326111953.31024-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 28b0c75587483dc7f7322d5407e4a97ab99ba031..236a675231e56641d6557bc02c959ae74b4b48bd 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -171,6 +171,240 @@
                        /* placeholder */
                };
 
+               eth0: ethernet@11c30000 {
+                       compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
+                       reg = <0 0x11c30000 0 0x10000>;
+                       interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+                                         "rx-queue-0", "rx-queue-1", "rx-queue-2",
+                                         "rx-queue-3", "tx-queue-0", "tx-queue-1",
+                                         "tx-queue-2", "tx-queue-3", "ptp-pps-0",
+                                         "ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
+                       clocks =  <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>,
+                                 <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>;
+                       clock-names = "stmmaceth", "pclk", "ptp_ref",
+                                     "tx", "rx", "tx-180", "rx-180",
+                                     "rmii", "rmii_tx", "rmii_rx";
+                       resets = <&cpg R9A08G046_ETH0_ARESET_N>;
+                       power-domains = <&cpg>;
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       rx-fifo-depth = <8192>;
+                       tx-fifo-depth = <8192>;
+                       snps,fixed-burst;
+                       snps,no-pbl-x8;
+                       snps,force_thresh_dma_mode;
+                       snps,axi-config = <&stmmac_axi_setup>;
+                       snps,mtl-rx-config = <&mtl_rx_setup0>;
+                       snps,mtl-tx-config = <&mtl_tx_setup0>;
+                       snps,txpbl = <32>;
+                       snps,rxpbl = <32>;
+                       status = "disabled";
+
+                       mdio0: mdio {
+                               compatible = "snps,dwmac-mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       mtl_rx_setup0: rx-queues-config {
+                               snps,rx-queues-to-use = <4>;
+                               snps,rx-sched-sp;
+
+                               queue0 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x1>;
+                                       snps,map-to-dma-channel = <0>;
+                               };
+
+                               queue1 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x2>;
+                                       snps,map-to-dma-channel = <1>;
+                               };
+
+                               queue2 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x4>;
+                                       snps,map-to-dma-channel = <2>;
+                               };
+
+                               queue3 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x8>;
+                                       snps,map-to-dma-channel = <3>;
+                               };
+                       };
+
+                       mtl_tx_setup0: tx-queues-config {
+                               snps,tx-queues-to-use = <4>;
+                               snps,tx-sched-wrr;
+
+                               queue0 {
+                                       snps,weight = <0x10>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x1>;
+                               };
+
+                               queue1 {
+                                       snps,weight = <0x12>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x2>;
+                               };
+
+                               queue2 {
+                                       snps,weight = <0x14>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x4>;
+                               };
+
+                               queue3 {
+                                       snps,weight = <0x18>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x8>;
+                               };
+                       };
+               };
+
+               eth1: ethernet@11c40000 {
+                       compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
+                       reg = <0 0x11c40000 0 0x10000>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+                                         "rx-queue-0", "rx-queue-1", "rx-queue-2",
+                                         "rx-queue-3", "tx-queue-0", "tx-queue-1",
+                                         "tx-queue-2", "tx-queue-3", "ptp-pps-0",
+                                         "ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
+                       clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>,
+                                <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>;
+                       clock-names = "stmmaceth", "pclk", "ptp_ref",
+                                     "tx", "rx", "tx-180", "rx-180",
+                                     "rmii", "rmii_tx", "rmii_rx";
+                       resets = <&cpg R9A08G046_ETH1_ARESET_N>;
+                       power-domains = <&cpg>;
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       rx-fifo-depth = <8192>;
+                       tx-fifo-depth = <8192>;
+                       snps,fixed-burst;
+                       snps,no-pbl-x8;
+                       snps,force_thresh_dma_mode;
+                       snps,axi-config = <&stmmac_axi_setup>;
+                       snps,mtl-rx-config = <&mtl_rx_setup1>;
+                       snps,mtl-tx-config = <&mtl_tx_setup1>;
+                       snps,txpbl = <32>;
+                       snps,rxpbl = <32>;
+                       status = "disabled";
+
+                       mdio1: mdio {
+                               compatible = "snps,dwmac-mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       mtl_rx_setup1: rx-queues-config {
+                               snps,rx-queues-to-use = <4>;
+                               snps,rx-sched-sp;
+
+                               queue0 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x1>;
+                                       snps,map-to-dma-channel = <0>;
+                               };
+
+                               queue1 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x2>;
+                                       snps,map-to-dma-channel = <1>;
+                               };
+
+                               queue2 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x4>;
+                                       snps,map-to-dma-channel = <2>;
+                               };
+
+                               queue3 {
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x8>;
+                                       snps,map-to-dma-channel = <3>;
+                               };
+                       };
+
+                       mtl_tx_setup1: tx-queues-config {
+                               snps,tx-queues-to-use = <4>;
+                               snps,tx-sched-wrr;
+
+                               queue0 {
+                                       snps,weight = <0x10>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x1>;
+                               };
+
+                               queue1 {
+                                       snps,weight = <0x12>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x2>;
+                               };
+
+                               queue2 {
+                                       snps,weight = <0x14>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x4>;
+                               };
+
+                               queue3 {
+                                       snps,weight = <0x18>;
+                                       snps,dcb-algorithm;
+                                       snps,priority = <0x8>;
+                               };
+                       };
+               };
+
                pcie: pcie@11e40000 {
                        reg = <0 0x11e40000 0 0x10000>;
                        ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
@@ -200,6 +434,13 @@
                };
        };
 
+       stmmac_axi_setup: stmmac-axi-config {
+               snps,lpi_en;
+               snps,wr_osr_lmt = <0xf>;
+               snps,rd_osr_lmt = <0xf>;
+               snps,blen = <16 8 4 0 0 0 0>;
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,