arm64: dts: qcom: Add PCIe3 and PCIe5 support for HAMOA-IOT-SOM platform

HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller
and SDX65.

Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states
and power supply properties in the device tree, which PCIe3 and PCIe5
require.

Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260109104504.3147745-3-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
index 4a69852e9176052a8b4f7242e9777234b766e141..81866f94fe01806953afa87a9e05d4594e0fea5e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
@@ -390,6 +390,20 @@
        firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
 };
 
+&pcie3 {
+       pinctrl-0 = <&pcie3_default>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie3_phy {
+       vdda-phy-supply = <&vreg_l3c_0p8>;
+       vdda-pll-supply = <&vreg_l3e_1p2>;
+
+       status = "okay";
+};
+
 &pcie4 {
        perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
        wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
@@ -407,6 +421,20 @@
        status = "okay";
 };
 
+&pcie5 {
+       pinctrl-0 = <&pcie5_default>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie5_phy {
+       vdda-phy-supply = <&vreg_l3i_0p8>;
+       vdda-pll-supply = <&vreg_l3e_1p2>;
+
+       status = "okay";
+};
+
 &pcie6a {
        perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
        wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
@@ -453,6 +481,29 @@
 &tlmm {
        gpio-reserved-ranges = <34 2>; /* TPM LP & INT */
 
+       pcie3_default: pcie3-default-state {
+               clkreq-n-pins {
+                       pins = "gpio144";
+                       function = "pcie3_clk";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio143";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-disable;
+               };
+
+               wake-n-pins {
+                       pins = "gpio145";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
        pcie4_default: pcie4-default-state {
                clkreq-n-pins {
                        pins = "gpio147";
@@ -476,6 +527,29 @@
                };
        };
 
+       pcie5_default: pcie5-default-state {
+               clkreq-n-pins {
+                       pins = "gpio150";
+                       function = "pcie5_clk";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio149";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-disable;
+               };
+
+               wake-n-pins {
+                       pins = "gpio151";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
        pcie6a_default: pcie6a-default-state {
                clkreq-n-pins {
                        pins = "gpio153";