arm64: dts: ti: k3-j722s-main: fix the audio refclk source

At the moment the clock parent of the audio extclk output is PLL1_HSDIV6
of the main domain. This very clock output is also used among various IP
cores, for example for the USB1 LPM clock. The audio extclock being an
external clock output with a variable frequency, it is likely that a
user of this clock will try to set it's frequency to a different value,
i.e. an audio codec. Because that clock output is used also for other IP
cores, bad things will happen.

Instead of using PLL1_HSDIV6 use the PLL2_HSDIV8 as a sane default, as
this output is exclusively used among other audio peripherals.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Link: https://patch.msgid.link/20251017102228.530517-2-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index d57fdd38bdceb7c4ca37b72767aafef0a07f5b17..7b7c25c2c6d9bc6684b4f8a78755182eb93e78e5 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -443,7 +443,7 @@
                reg = <0x82e0 0x4>;
                clocks = <&k3_clks 157 0>;
                assigned-clocks = <&k3_clks 157 0>;
-               assigned-clock-parents = <&k3_clks 157 15>;
+               assigned-clock-parents = <&k3_clks 157 16>;
                #clock-cells = <0>;
        };
 
@@ -452,7 +452,7 @@
                reg = <0x82e4 0x4>;
                clocks = <&k3_clks 157 18>;
                assigned-clocks = <&k3_clks 157 18>;
-               assigned-clock-parents = <&k3_clks 157 33>;
+               assigned-clock-parents = <&k3_clks 157 34>;
                #clock-cells = <0>;
        };
 };