drm/i915/dg1: Update DMC_DEBUG3 register

[ Upstream commit b60668cb4c57a7cc451de781ae49f5e9cc375eaf ]

Current DMC_DEBUG3(_MMIO(0x101090)) address is for TGL,
it is wrong for DG1. Just like commit 5bcc95ca382e
("drm/i915/dg1: Update DMC_DEBUG register"), correct
this issue for DG1 platform to avoid wrong register
being read.

BSpec: 49788

v2: fix "not wrong" typo. (Jani)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Chuansheng Liu <chuansheng.liu@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220211002933.84240-1-chuansheng.liu@intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0bf31f9a8af56b1d3640a1839d1da59d30cd8a20..e6780fcc5006fd47db457ba3de8809685ec76335 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -526,8 +526,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
                 * reg for DC3CO debugging and validation,
                 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
                 */
-               seq_printf(m, "DC3CO count: %d\n",
-                          intel_de_read(dev_priv, DMC_DEBUG3));
+               seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, IS_DGFX(dev_priv) ?
+                                       DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
        } else {
                dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
                                                 SKL_CSR_DC3_DC5_COUNT;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1ab26307db6f1de504a8bc5c02147a032bdce6f..04157d8ced3206ff8d23ec742c682bc3b902c3b7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7546,7 +7546,8 @@ enum {
 #define TGL_DMC_DEBUG_DC5_COUNT        _MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT        _MMIO(0x101088)
 
-#define DMC_DEBUG3             _MMIO(0x101090)
+#define TGL_DMC_DEBUG3         _MMIO(0x101090)
+#define DG1_DMC_DEBUG3         _MMIO(0x13415c)
 
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT             _MMIO(0x42060)