arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4B

Enable USB3 OTG and it's related PHY node. And the PHY will
also be shared with the upcoming DisplayPort controller.

Signed-off-by: Andy Yan <andyshrk@163.com>
Link: https://lore.kernel.org/r/20250223100757.73531-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
index f471baca6d3101ce7e850b666589587dc70d8a17..e3c6dd9b95cf12e13289a170ca64f12c74d2acbb 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
@@ -803,6 +803,14 @@
        status = "okay";
 };
 
+&u2phy0 {
+       status = "okay";
+};
+
+&u2phy0_otg {
+       status = "okay";
+};
+
 &u2phy2 {
        status = "okay";
 };
@@ -832,6 +840,16 @@
        pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
 };
 
+&usbdp_phy0 {
+       /*
+        * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally
+        * the differential pairs 0+1 and the aux channel are wired to a
+        * mini DP connector.
+        */
+       rockchip,dp-lane-mux = <0 1>;
+       status = "okay";
+};
+
 &usb_host0_ehci {
        status = "okay";
 };
@@ -840,6 +858,11 @@
        status = "okay";
 };
 
+&usb_host0_xhci {
+       extcon = <&u2phy0>;
+       status = "okay";
+};
+
 &usb_host1_ehci {
        status = "okay";
 };