#define SI1133_MAX_CMD_CTR 0xF
#define SI1133_PARAM_REG_CHAN_LIST 0x01
-#define SI1133_PARAM_REG_ADCCONFIG(x) ((x) * 4) + 2
-#define SI1133_PARAM_REG_ADCSENS(x) ((x) * 4) + 3
-#define SI1133_PARAM_REG_ADCPOST(x) ((x) * 4) + 4
+#define SI1133_PARAM_REG_ADCCONFIG(x) (((x) * 4) + 2)
+#define SI1133_PARAM_REG_ADCSENS(x) (((x) * 4) + 3)
+#define SI1133_PARAM_REG_ADCPOST(x) (((x) * 4) + 4)
#define SI1133_ADCMUX_MASK 0x1F
-#define SI1133_ADCCONFIG_DECIM_RATE(x) (x) << 5
+#define SI1133_ADCCONFIG_DECIM_RATE(x) ((x) << 5)
#define SI1133_ADCSENS_SCALE_MASK 0x70
#define SI1133_ADCSENS_SCALE_SHIFT 4
#define SI1133_ADCSENS_HSIG_MASK BIT(7)
#define SI1133_ADCSENS_HSIG_SHIFT 7
#define SI1133_ADCSENS_HW_GAIN_MASK 0xF
-#define SI1133_ADCSENS_NB_MEAS(x) fls(x) << SI1133_ADCSENS_SCALE_SHIFT
+#define SI1133_ADCSENS_NB_MEAS(x) (fls(x) << SI1133_ADCSENS_SCALE_SHIFT)
#define SI1133_ADCPOST_24BIT_EN BIT(6)
-#define SI1133_ADCPOST_POSTSHIFT_BITQTY(x) (x & GENMASK(2, 0)) << 3
+#define SI1133_ADCPOST_POSTSHIFT_BITQTY(x) (((x) & GENMASK(2, 0)) << 3)
#define SI1133_PARAM_ADCMUX_SMALL_IR 0x0
#define SI1133_PARAM_ADCMUX_MED_IR 0x1
#define SI1133_CMD_MINSLEEP_US_HIGH 7500
#define SI1133_CMD_TIMEOUT_MS 25
-#define SI1133_REG_HOSTOUT(x) (x) + 0x13
+#define SI1133_REG_HOSTOUT(x) ((x) + 0x13)
#define SI1133_X_ORDER_MASK 0x0070
#define SI1133_Y_ORDER_MASK 0x0007
-#define si1133_get_x_order(m) ((m) & SI1133_X_ORDER_MASK) >> 4
+#define si1133_get_x_order(m) (((m) & SI1133_X_ORDER_MASK) >> 4)
#define si1133_get_y_order(m) ((m) & SI1133_Y_ORDER_MASK)
#define SI1133_LUX_ADC_MASK 0xE