mips64: support for prctl(GET/SET_FP_MODE) syscalls

Adding a program (change_fp_mode) to test correct fpu emulation and
fp mode switch using prctl syscalls.

Patch by Aleksandar Rikalo.
Related bug - BZ #366079.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16004

diff --git a/none/tests/mips64/Makefile.am b/none/tests/mips64/Makefile.am
index 2876030afef5bdf252183e6d249e820cd7b3b315..3c603a0eb5d709ac35eb297533f11aea34cbbc1f 100644 (file)
--- a/none/tests/mips64/Makefile.am
+++ b/none/tests/mips64/Makefile.am
@@ -10,6 +10,7 @@ EXTRA_DIST = \
        branch_and_jump_instructions.stdout.exp \
        branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \
        branches.stdout.exp branches.stderr.exp branches.vgtest \
+       change_fp_mode.stderr.exp change_fp_mode.stdout.exp change_fp_mode.vgtest \
        cvm_bbit.stdout.exp cvm_bbit.stdout.exp-non-octeon \
        cvm_bbit.stderr.exp cvm_bbit.vgtest \
        cvm_ins.stdout.exp cvm_ins.stdout.exp-non-octeon \
@@ -65,6 +66,7 @@ check_PROGRAMS = \
        arithmetic_instruction \
        branch_and_jump_instructions \
        branches \
+       change_fp_mode \
        cvm_bbit \
        cvm_ins \
        cvm_lx_ins \

diff --git a/none/tests/mips64/change_fp_mode.c b/none/tests/mips64/change_fp_mode.c
new file mode 100644 (file)
index 0000000..fb29365
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.c
@@ -0,0 +1,259 @@
+#include <elf.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/prctl.h>
+
+#if !defined(PR_SET_FP_MODE)
+#   define PR_SET_FP_MODE 45
+#endif
+
+#if !defined(PR_GET_FP_MODE)
+#   define PR_GET_FP_MODE 46
+#endif
+
+#define TEST_LD(instruction, source)                              \
+{                                                                 \
+   unsigned int result1, result2;                                 \
+   __asm__ volatile(                                              \
+      ".set push\n\t"                                             \
+      ".set noreorder\n\t"                                        \
+      "li $t0, 0x5a5a\n\t"                                        \
+      "mtc1 $t0, $f0\n\t"                                         \
+      "mtc1 $t0, $f1\n\t"                                         \
+      "move $t0, %2\n\t"                                          \
+      instruction"\n\t"                                           \
+      "swc1 $f0, %0\n\t"                                          \
+      "swc1 $f1, %1\n\t"                                          \
+      ".set pop\n\t"                                              \
+      : "=m"(result1), "=m"(result2)                              \
+      : "r" (&source)                                             \
+      : "t0", "$f0", "$f1");                                      \
+   printf(instruction" :: lo32(f1): %x, lo32(f0): %x\n",          \
+          result2, result1);                                      \
+}
+
+#define _TEST_ST(instruction)                                     \
+   __asm__ volatile(                                              \
+      ".set push\n\t"                                             \
+      ".set noreorder\n\t"                                        \
+      "li $t0, 0x5a5a\n\t"                                        \
+      "dmtc1 $t0, $f1\n\t"                                        \
+      "move $t0, %0\n\t"                                          \
+      "ldc1 $f0, 0($t0)\n\t"                                      \
+      "move $t0, %1\n\t"                                          \
+      instruction"\n\t"                                           \
+      ".set pop\n\t"                                              \
+      :                                                           \
+      : "r" (&source64), "r" (&result)                            \
+      : "t0", "$f0", "$f1", "memory")
+
+#define TEST_ST64(instruction)                                    \
+{                                                                 \
+   unsigned long result;                                          \
+   _TEST_ST(instruction);                                         \
+   printf(instruction" :: mem: %lx\n", result);                   \
+}
+
+#define TEST_ST32(instruction)                                    \
+{                                                                 \
+   unsigned int result;                                           \
+   _TEST_ST(instruction);                                         \
+   printf(instruction" :: mem: %x\n", result);                    \
+}
+
+#define TEST_MT(instruction)                                      \
+{                                                                 \
+   unsigned int result1, result2;                                 \
+   __asm__ volatile(                                              \
+      ".set push\n\t"                                             \
+      ".set noreorder\n\t"                                        \
+      "li $t0, 0x5a5a\n\t"                                        \
+      "mtc1 $t0, $f0\n\t"                                         \
+      "mtc1 $t0, $f1\n\t"                                         \
+      "ld $t0, %2\n\t"                                            \
+      instruction"\n\t"                                           \
+      "swc1 $f0, %0\n\t"                                          \
+      "swc1 $f1, %1\n\t"                                          \
+      ".set pop\n\t"                                              \
+      : "=m"(result1), "=m"(result2)                              \
+      : "m" (source64)                                            \
+      : "t0", "$f0", "$f1");                                      \
+   printf(instruction" :: lo32(f1): %x, lo32(f0): %x\n",          \
+          result2, result1);                                      \
+}
+
+#define TEST_MF(instruction)                                      \
+{                                                                 \
+   unsigned long result;                                          \
+   __asm__ volatile(                                              \
+      ".set push\n\t"                                             \
+      ".set noreorder\n\t"                                        \
+      "li $t0, 0x5a5a\n\t"                                        \
+      "dmtc1 $t0, $f1\n\t"                                        \
+      "ldc1 $f0, %1\n\t"                                          \
+      "move $t0, $0\n\t"                                          \
+      instruction"\n\t"                                           \
+      "sd $t0, %0\n\t"                                            \
+      ".set pop\n\t"                                              \
+      : "=m" (result)                                             \
+      : "m" (source64)                                            \
+      : "t0", "$f0", "$f1");                                      \
+   printf(instruction" :: t0: %lx\n", result);                    \
+}
+
+#define TEST_MOVE(instruction)                                    \
+{                                                                 \
+   unsigned int result1, result2;                                 \
+   __asm__ volatile(                                              \
+      ".set push\n\t"                                             \
+      ".set noreorder\n\t"                                        \
+      "li $t0, 0x5a5a\n\t"                                        \
+      "mtc1 $t0, $f0\n\t"                                         \
+      "li $t0, 0x6b6b\n\t"                                        \
+      "mtc1 $t0, $f1\n\t"                                         \
+      "li $t0, 0x7c7c\n\t"                                        \
+      "dmtc1 $t0, $f2\n\t"                                        \
+      "ldc1 $f2, %2\n\t"                                          \
+      instruction"\n\t"                                           \
+      "swc1 $f0, %0\n\t"                                          \
+      "swc1 $f1, %1\n\t"                                          \
+      ".set pop\n\t"                                              \
+      : "=m"(result1), "=m"(result2)                              \
+      : "m" (source64)                                            \
+      : "t0", "$f0", "$f1", "$f2");                               \
+   printf(instruction" :: lo32(f1): %x, lo32(f0): %x\n",          \
+          result2, result1);                                      \
+}
+
+unsigned long source64 = 0x1234567890abcdefull;
+unsigned int  source32 = 0x12345678u;
+
+/* Determine FP mode based on sdc1 behavior
+   returns 1 if FR = 1 mode is detected (assumes FRE = 0) */
+static int get_fp_mode(void) {
+   unsigned long result = 0;
+   __asm__ volatile(
+      ".set push\n\t"
+      ".set noreorder\n\t"
+      "lui $t0, 0x3ff0\n\t"
+      "ldc1 $f0, %0\n\t"
+      "mtc1 $t0, $f1\n\t"
+      "sdc1 $f0, %0\n\t"
+      ".set pop\n\t"
+      : "+m"(result)
+      :
+      : "t0", "$f0", "$f1", "memory");
+
+   return (result != 0x3ff0000000000000ull);
+}
+
+static void fatal_error(const char* msg) {
+   fprintf(stderr, "Error: %s\n", msg);
+   exit(1);
+}
+
+static void test(int* fr_prctl, int* fr_detected) {
+
+   *fr_prctl = prctl(PR_GET_FP_MODE);
+   *fr_detected = get_fp_mode();
+
+   if (*fr_prctl < 0) {
+      fatal_error("prctl(PR_GET_FP_MODE) fails.");
+   }
+
+   printf("fr_prctl: %d, fr_detected: %d\n", *fr_prctl, *fr_detected);
+
+   if (*fr_prctl != *fr_detected) {
+      fatal_error("fr_prctl != fr_detected");
+   }
+
+   TEST_LD("lwc1 $f0, 0($t0)", source32);
+   TEST_LD("lwc1 $f1, 0($t0)", source32);
+
+   TEST_LD("lwxc1 $f0, $0($t0)", source32);
+   TEST_LD("lwxc1 $f1, $0($t0)", source32);
+
+   TEST_LD("ldc1 $f0, 0($t0)", source64);
+   TEST_LD("ldc1 $f1, 0($t0)", source64);
+
+   TEST_LD("ldxc1 $f0, $0($t0)", source64);
+   TEST_LD("ldxc1 $f1, $0($t0)", source64);
+
+   TEST_ST32("swc1 $f0, 0($t0)");
+   TEST_ST32("swc1 $f1, 0($t0)");
+
+   TEST_ST32("swxc1 $f0, $0($t0)");
+   TEST_ST32("swxc1 $f1, $0($t0)");
+
+   TEST_ST64("sdc1 $f0, 0($t0)");
+   TEST_ST64("sdc1 $f1, 0($t0)");
+
+   TEST_ST64("sdxc1 $f0, $0($t0)");
+   TEST_ST64("sdxc1 $f1, $0($t0)");
+
+   TEST_MT("mtc1 $t0, $f0");
+   TEST_MT("mtc1 $t0, $f1");
+
+   TEST_MT("dmtc1 $t0, $f0");
+   TEST_MT("dmtc1 $t0, $f1");
+
+   TEST_MF("mfc1 $t0, $f0");
+   TEST_MF("mfc1 $t0, $f1");
+
+   TEST_MF("dmfc1 $t0, $f0");
+   TEST_MF("dmfc1 $t0, $f1");
+
+   TEST_MOVE("movn.s $f0, $f2, $t0");
+   TEST_MOVE("movn.s $f0, $f1, $t0");
+   TEST_MOVE("movn.s $f1, $f2, $t0");
+   TEST_MOVE("movn.s $f0, $f2, $0");
+   TEST_MOVE("movn.s $f0, $f1, $0");
+   TEST_MOVE("movn.s $f1, $f2, $0");
+
+   TEST_MOVE("movn.d $f0, $f2, $t0");
+   TEST_MOVE("movn.d $f0, $f1, $t0");
+   TEST_MOVE("movn.d $f1, $f2, $t0");
+   TEST_MOVE("movn.d $f0, $f2, $0");
+   TEST_MOVE("movn.d $f0, $f1, $0");
+   TEST_MOVE("movn.d $f1, $f2, $0");
+
+   TEST_MOVE("movz.s $f0, $f2, $t0");
+   TEST_MOVE("movz.s $f0, $f1, $t0");
+   TEST_MOVE("movz.s $f1, $f2, $t0");
+   TEST_MOVE("movz.s $f0, $f2, $0");
+   TEST_MOVE("movz.s $f0, $f1, $0");
+   TEST_MOVE("movz.s $f1, $f2, $0");
+
+   TEST_MOVE("movz.d $f0, $f2, $t0");
+   TEST_MOVE("movz.d $f0, $f1, $t0");
+   TEST_MOVE("movz.d $f1, $f2, $t0");
+   TEST_MOVE("movz.d $f0, $f2, $0");
+   TEST_MOVE("movz.d $f0, $f1, $0");
+   TEST_MOVE("movz.d $f1, $f2, $0");
+}
+
+int main() {
+   int fr_prctl, fr_detected;
+
+   test(&fr_prctl, &fr_detected);
+
+   /* FP64 */
+   if (fr_prctl == 1) {
+
+      /* Change mode to FP32 */
+      if (prctl(PR_SET_FP_MODE, 0) != 0) {
+         fatal_error("prctl(PR_SET_FP_MODE, 0) fails.");
+      }
+
+      test(&fr_prctl, &fr_detected);
+
+      /* Change back FP mode */
+      if (prctl(PR_SET_FP_MODE, 1) != 0) {
+         fatal_error("prctl(PR_SET_FP_MODE, 1) fails.");
+      }
+
+      test(&fr_prctl, &fr_detected);
+   }
+
+   return 0;
+}

diff --git a/none/tests/mips64/change_fp_mode.stderr.exp b/none/tests/mips64/change_fp_mode.stderr.exp
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/none/tests/mips64/change_fp_mode.stdout.exp b/none/tests/mips64/change_fp_mode.stdout.exp
new file mode 100644 (file)
index 0000000..f527e1e
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.stdout.exp
@@ -0,0 +1,147 @@
+fr_prctl: 1, fr_detected: 1
+lwc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+lwxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+ldc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldc1 $f1, 0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+ldxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldxc1 $f1, $0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+swc1 $f0, 0($t0) :: mem: 90abcdef
+swc1 $f1, 0($t0) :: mem: 5a5a
+swxc1 $f0, $0($t0) :: mem: 90abcdef
+swxc1 $f1, $0($t0) :: mem: 5a5a
+sdc1 $f0, 0($t0) :: mem: 1234567890abcdef
+sdc1 $f1, 0($t0) :: mem: 5a5a
+sdxc1 $f0, $0($t0) :: mem: 1234567890abcdef
+sdxc1 $f1, $0($t0) :: mem: 5a5a
+mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+mfc1 $t0, $f0 :: t0: ffffffff90abcdef
+mfc1 $t0, $f1 :: t0: 5a5a
+dmfc1 $t0, $f0 :: t0: 1234567890abcdef
+dmfc1 $t0, $f1 :: t0: 5a5a
+movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.d $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.d $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+fr_prctl: 0, fr_detected: 0
+lwc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+lwxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+ldc1 $f0, 0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+ldc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+ldxc1 $f0, $0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+ldxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+swc1 $f0, 0($t0) :: mem: 90abcdef
+swc1 $f1, 0($t0) :: mem: 12345678
+swxc1 $f0, $0($t0) :: mem: 90abcdef
+swxc1 $f1, $0($t0) :: mem: 12345678
+sdc1 $f0, 0($t0) :: mem: 1234567890abcdef
+sdc1 $f1, 0($t0) :: mem: 1234567890abcdef
+sdxc1 $f0, $0($t0) :: mem: 1234567890abcdef
+sdxc1 $f1, $0($t0) :: mem: 1234567890abcdef
+mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+dmtc1 $t0, $f0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+dmtc1 $t0, $f1 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+mfc1 $t0, $f0 :: t0: ffffffff90abcdef
+mfc1 $t0, $f1 :: t0: 12345678
+dmfc1 $t0, $f0 :: t0: 1234567890abcdef
+dmfc1 $t0, $f1 :: t0: 1234567890abcdef
+movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f2, $t0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $t0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f2, $0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+movz.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+fr_prctl: 1, fr_detected: 1
+lwc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+lwxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+ldc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldc1 $f1, 0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+ldxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldxc1 $f1, $0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+swc1 $f0, 0($t0) :: mem: 90abcdef
+swc1 $f1, 0($t0) :: mem: 5a5a
+swxc1 $f0, $0($t0) :: mem: 90abcdef
+swxc1 $f1, $0($t0) :: mem: 5a5a
+sdc1 $f0, 0($t0) :: mem: 1234567890abcdef
+sdc1 $f1, 0($t0) :: mem: 5a5a
+sdxc1 $f0, $0($t0) :: mem: 1234567890abcdef
+sdxc1 $f1, $0($t0) :: mem: 5a5a
+mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+mfc1 $t0, $f0 :: t0: ffffffff90abcdef
+mfc1 $t0, $f1 :: t0: 5a5a
+dmfc1 $t0, $f0 :: t0: 1234567890abcdef
+dmfc1 $t0, $f1 :: t0: 5a5a
+movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.d $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.d $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a

diff --git a/none/tests/mips64/change_fp_mode.vgtest b/none/tests/mips64/change_fp_mode.vgtest
new file mode 100644 (file)
index 0000000..68fa456
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.vgtest
@@ -0,0 +1,2 @@
+prog: change_fp_mode
+vgopts: -q