Limit threads sharing L2 cache to 2 for SLM/KNL

Silvermont and Knights Landing have a modular system design with two cores
sharing an L2 cache.  If more than 2 cores are detected to shared L2 cache,
it should be adjusted for Silvermont and Knights Landing.

	[BZ #18185]
	* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
	sharing L2 cache to 2 for Silvermont/Knights Landing.

diff --git a/ChangeLog b/ChangeLog
index dd40484e70dcb8b81b29576b5caef8f4b02c2b3c..3e8df42d31ba86db8a64bddcc82dd945da4a21f1 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+       [BZ #18185]
+       * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
+       sharing L2 cache to 2 for Silvermont/Knights Landing.
+
 2015-03-31  H.J. Lu  <hongjiu.lu@intel.com>
 
        [BZ #17711]

diff --git a/NEWS b/NEWS
index b66c1b1daaae7c07255545d35fd55bda7a3857bb..d2651b3a8d8336f1b2131a2b221d976e7fa5a6b8 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -15,7 +15,7 @@ Version 2.22
   17932, 17944, 17949, 17964, 17965, 17967, 17969, 17978, 17987, 17991,
   17996, 17998, 17999, 18019, 18020, 18029, 18030, 18032, 18036, 18038,
   18039, 18042, 18043, 18046, 18047, 18068, 18080, 18093, 18100, 18104,
-  18110, 18111, 18128, 18138.
+  18110, 18111, 18128, 18138, 18185.
 
 * A powerpc and powerpc64 optimization for TLS, similar to TLS descriptors
   for LD and GD on x86 and x86-64, has been implemented.  You will need

diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index f1cbf50957cfc454f8b55bde2608ab8c0a46737f..b99fb9a762c0ce77faada607bea137e224de94ac 100644 (file)
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -585,6 +585,10 @@ init_cacheinfo (void)
       __cpuid (1, eax, ebx_1, ecx, edx);
 #endif
 
+      unsigned int family = (eax >> 8) & 0x0f;
+      unsigned int model = (eax >> 4) & 0x0f;
+      unsigned int extended_model = (eax >> 12) & 0xf0;
+
 #ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
       /* Intel prefers SSSE3 instructions for memory/string routines
         if they are available.  */
@@ -647,6 +651,25 @@ init_cacheinfo (void)
                }
            }
          threads += 1;
+         if (threads > 2 && level == 2 && family == 6)
+           {
+             model += extended_model;
+             switch (model)
+               {
+               case 0x57:
+                 /* Knights Landing has L2 cache shared by 2 cores.  */
+               case 0x37:
+               case 0x4a:
+               case 0x4d:
+               case 0x5a:
+               case 0x5d:
+                 /* Silvermont has L2 cache shared by 2 cores.  */
+                 threads = 2;
+                 break;
+               default:
+                 break;
+               }
+           }
        }
       else
        {