clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL

Add clock ops for Rivian ELU and EKO_T PLLs, add the register offsets
for the Rivian ELU PLL. Since ELU and EKO_T shared the same offsets and
PLL ops, reuse the Rivian EKO_T enum.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-3-8e10adc236a8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 6aeba40358c11e44c5f39d15f149d62149393cd3..8586649d76f8aef119ed51fbf1ca90bc5e3ce510 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -243,6 +243,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
                [PLL_OFF_TEST_CTL] = 0x28,
                [PLL_OFF_TEST_CTL_U] = 0x2c,
        },
+       [CLK_ALPHA_PLL_TYPE_RIVIAN_ELU] = {
+               [PLL_OFF_OPMODE] = 0x04,
+               [PLL_OFF_STATUS] = 0x0c,
+               [PLL_OFF_L_VAL] = 0x10,
+               [PLL_OFF_USER_CTL] = 0x14,
+               [PLL_OFF_USER_CTL_U] = 0x18,
+               [PLL_OFF_CONFIG_CTL] = 0x1c,
+               [PLL_OFF_CONFIG_CTL_U] = 0x20,
+               [PLL_OFF_CONFIG_CTL_U1] = 0x24,
+               [PLL_OFF_CONFIG_CTL_U2] = 0x28,
+               [PLL_OFF_TEST_CTL] = 0x2c,
+               [PLL_OFF_TEST_CTL_U] = 0x30,
+       },
        [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
                [PLL_OFF_L_VAL] = 0x04,
                [PLL_OFF_ALPHA_VAL] = 0x08,
@@ -3002,6 +3015,7 @@ void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
                clk_taycan_elu_pll_configure(pll, regmap, pll->config);
                break;
        case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO:
+       case CLK_ALPHA_PLL_TYPE_RIVIAN_ELU:
                clk_rivian_evo_pll_configure(pll, regmap, pll->config);
                break;
        case CLK_ALPHA_PLL_TYPE_TRION:

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 0903a05b18ccc68c9f8de5c7405bb197bf8d3d1d..046e6f2583ea83b4478765f41e518cb5c234079f 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -31,6 +31,8 @@ enum {
        CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
        CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
        CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
+       CLK_ALPHA_PLL_TYPE_RIVIAN_ELU,
+       CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T = CLK_ALPHA_PLL_TYPE_RIVIAN_ELU,
        CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
        CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
        CLK_ALPHA_PLL_TYPE_STROMER,
@@ -208,6 +210,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
 extern const struct clk_ops clk_alpha_pll_pongo_elu_ops;
 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
+#define clk_alpha_pll_rivian_elu_ops clk_alpha_pll_rivian_evo_ops
+#define clk_alpha_pll_rivian_eko_t_ops clk_alpha_pll_rivian_evo_ops
 
 extern const struct clk_ops clk_alpha_pll_regera_ops;
 extern const struct clk_ops clk_alpha_pll_slew_ops;