struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, i);
struct irq_desc *desc;
unsigned long flags;
+ bool pending;
int ret;
raw_spin_lock_irqsave(&irq->irq_lock, flags);
irq->hw = false;
ret = irq_get_irqchip_state(irq->host_irq,
IRQCHIP_STATE_PENDING,
- &irq->pending_latch);
+ &pending);
WARN_ON(ret);
+ irq->pending_latch = pending;
+
desc = irq_to_desc(irq->host_irq);
irq_domain_deactivate_irq(irq_desc_get_irq_data(desc));
unlock:
struct vgic_irq {
raw_spinlock_t irq_lock; /* Protects the content of the struct */
+ u32 intid; /* Guest visible INTID */
struct rcu_head rcu;
struct list_head ap_list;
* affinity reg (v3).
*/
- u32 intid; /* Guest visible INTID */
- bool line_level; /* Level only */
- bool pending_latch; /* The pending latch state used to calculate
- * the pending state for both level
- * and edge triggered IRQs. */
- bool active;
- bool pending_release; /* Used for LPIs only, unreferenced IRQ
+ bool pending_release:1; /* Used for LPIs only, unreferenced IRQ
* pending a release */
- bool enabled;
- bool hw; /* Tied to HW IRQ */
+ bool pending_latch:1; /* The pending latch state used to calculate
+ * the pending state for both level
+ * and edge triggered IRQs. */
+ enum vgic_irq_config config:1; /* Level or edge */
+ bool line_level:1; /* Level only */
+ bool enabled:1;
+ bool active:1;
+ bool hw:1; /* Tied to HW IRQ */
refcount_t refcount; /* Used for LPIs */
u32 hwintid; /* HW INTID number */
unsigned int host_irq; /* linux irq corresponding to hwintid */
u8 active_source; /* GICv2 SGIs only */
u8 priority;
u8 group; /* 0 == group 0, 1 == group 1 */
- enum vgic_irq_config config; /* Level or edge */
struct irq_ops *ops;