testsuite: Fix Advanced SIMD failures for SVE

This patch just adds some missing +nosve directives to Advanced
SIMD vectorisation tests.

gcc/testsuite/
	* gcc.target/aarch64/asimd-mull-elem.c: Add +nosve.
	* gcc.target/aarch64/pr98772.c: Likewise.
	* gcc.target/aarch64/simd/vect_su_add_sub.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c b/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c
index 513721cee0c8372781e6daf33bc06e256cab8cb8..8ee7d118251d1f7c17f228a182afd065d8596415 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c
+++ b/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c
@@ -3,6 +3,8 @@
 /* { dg-require-effective-target vect_float } */
 /* { dg-options "-Ofast" } */
 
+#pragma GCC target "+nosve"
+
 #include <arm_neon.h>
 
 void s_mult_i (int32_t* restrict res, int32_t* restrict a, int32_t b)

diff --git a/gcc/testsuite/gcc.target/aarch64/pr98772.c b/gcc/testsuite/gcc.target/aarch64/pr98772.c
index 663221514e9555f607231835c8c8435f956c7757..8259251a7c0b64ae8362ea29ec3cf1d2a9d63547 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/pr98772.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr98772.c
@@ -1,5 +1,8 @@
 /* { dg-do run } */
 /* { dg-options "-O3 -save-temps" } */
+
+#pragma GCC target "+nosve"
+
 #include <stdint.h>
 #include <string.h>
 

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c
index 921c5f15c74ce02d106f9b5290244532fc56d480..4abb8e92cb43e140600caa7d6f3fba3614247783 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c
@@ -1,6 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 typedef int __attribute__ ((mode (SI))) int32_t;
 typedef int __attribute__ ((mode (DI))) int64_t;
 typedef unsigned __attribute__ ((mode (SI))) size_t;