u32 logic_power_switch0_delay;
u32 logic_power_switch1_delay;
u32 off2on_delay;
+ bool has_rst_clk;
};
struct sunxi_pck600_pd {
if (IS_ERR(base))
return PTR_ERR(base);
- rst = devm_reset_control_get_exclusive_released(dev, NULL);
- if (IS_ERR(rst))
- return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
+ if (desc->has_rst_clk) {
+ rst = devm_reset_control_get_exclusive_released(dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
+ }
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
.device_ctrl1_delay = 0xffff,
.logic_power_switch0_delay = 0x8080808,
.logic_power_switch1_delay = 0x808,
- .off2on_delay = 0x8
+ .off2on_delay = 0x8,
+ .has_rst_clk = true,
+};
+
+static const char * const sun60i_a733_pck600_pd_names[] = {
+ "VI", "DE_SYS", "VE_DEC", "VE_ENC", "NPU",
+ "GPU_TOP", "GPU_CORE", "PCIE", "USB2", "VO", "VO1"
+};
+
+static const struct sunxi_pck600_desc sun60i_a733_pck600_desc = {
+ .pd_names = sun60i_a733_pck600_pd_names,
+ .num_domains = ARRAY_SIZE(sun60i_a733_pck600_pd_names),
+ .logic_power_switch0_delay_offset = 0xc00,
+ .logic_power_switch1_delay_offset = 0xc04,
+ .off2on_delay_offset = 0xc10,
+ .device_ctrl0_delay = 0x1f1f1f,
+ .device_ctrl1_delay = 0x1f1f,
+ .logic_power_switch0_delay = 0x8080808,
+ .logic_power_switch1_delay = 0x808,
+ .off2on_delay = 0x8,
+ .has_rst_clk = false,
};
static const struct of_device_id sunxi_pck600_of_match[] = {
.compatible = "allwinner,sun55i-a523-pck-600",
.data = &sun55i_a523_pck600_desc,
},
+ {
+ .compatible = "allwinner,sun60i-a733-pck-600",
+ .data = &sun60i_a733_pck600_desc,
+ },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_pck600_of_match);