tools/testing/cxl: Fix root port to host bridge assignment

Mocked root-ports are meant to be round-robin assigned to host-bridges.

Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy")
Link: https://lore.kernel.org/r/164298431629.3018233.14004377108116384485.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index cd2f20f2707fa026a902ed4c5fd2602348719f42..7e4a0b1ee436376a532581b7cdc3c6a4bbd1bf18 100644 (file)
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -558,7 +558,7 @@ static __init int cxl_test_init(void)
 
        for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) {
                struct platform_device *bridge =
-                       cxl_host_bridge[i / NR_CXL_ROOT_PORTS];
+                       cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)];
                struct platform_device *pdev;
 
                pdev = platform_device_alloc("cxl_root_port", i);