sparc.c (sparc_emit_membar_for_model): Add the implied StoreLoad barrier for atomic...

	* config/sparc/sparc.c (sparc_emit_membar_for_model) <SMM_TSO>: Add
	the implied StoreLoad barrier for atomic operations if before.

From-SVN: r201452

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cca738fbeacf12aa9ba0222a8aaf59cca28bf8f5..3ebc9e5664b3ff0cb278c8450d209997f2240233 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-08-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * config/sparc/sparc.c (sparc_emit_membar_for_model) <SMM_TSO>: Add
+       the implied StoreLoad barrier for atomic operations if before.
+
 2013-07-11  Georg-Johann Lay  <avr@gjlay.de>
 
        Backport from 2013-07-11 trunk r200901.

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 4f8e96f66542b3961d30bc00bc5fc2037308ef6b..8946b309fb51617610ff4c4a701545c8aa158b8c 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -10929,6 +10929,11 @@ sparc_emit_membar_for_model (enum memmodel model,
       /* Total Store Ordering: all memory transactions with store semantics
         are followed by an implied StoreStore.  */
       implied |= StoreStore;
+
+      /* If we're not looking for a raw barrer (before+after), then atomic
+        operations get the benefit of being both load and store.  */
+      if (load_store == 3 && before_after == 1)
+       implied |= StoreLoad;
       /* FALLTHRU */
 
     case SMM_PSO: