More reduction rules, which further reduce memcheck's false error

rate on optimised x86 and amd64 code.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1642

diff --git a/VEX/priv/guest-amd64/ghelpers.c b/VEX/priv/guest-amd64/ghelpers.c
index d500d765ba7c62e9ee4203ad6ab6d5e8815b65eb..19b40ac78ce6fceb5fab15c965ffc333c5009426 100644 (file)
--- a/VEX/priv/guest-amd64/ghelpers.c
+++ b/VEX/priv/guest-amd64/ghelpers.c
@@ -958,12 +958,6 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name,
                            binop(Iop_Shl64,cc_dep2,mkU8(32))));
       }
 
-//..       if (isU32(cc_op, AMD64G_CC_OP_SUBL) && isU32(cond, X86CondNZ)) {
-//..          /* long sub/cmp, then NZ --> test dst!=src */
-//..          return unop(Iop_1Uto32,
-//..                      binop(Iop_CmpNE32, cc_dep1, cc_dep2));
-//..       }
-
       if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondL)) {
          /* long sub/cmp, then L (signed less than) 
             --> test dst <s src */
@@ -992,12 +986,15 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name,
                            binop(Iop_Shl64,cc_dep2,mkU8(32))));
       }
 
-//..       if (isU32(cc_op, AMD64G_CC_OP_SUBL) && isU32(cond, X86CondB)) {
-//..          /* long sub/cmp, then B (unsigned less than)
-//..             --> test dst <u src */
-//..          return unop(Iop_1Uto32,
-//..                      binop(Iop_CmpLT32U, cc_dep1, cc_dep2));
-//..       }
+      if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondNBE)) {
+         /* long sub/cmp, then NBE (unsigned greater than)
+            --> test src <u dst */
+         /* Note, args are opposite way round from the usual */
+         return unop(Iop_1Uto64,
+                     binop(Iop_CmpLT64U, 
+                           binop(Iop_Shl64,cc_dep2,mkU8(32)),
+                           binop(Iop_Shl64,cc_dep1,mkU8(32))));
+      }
 
       /*---------------- SUBW ----------------*/
 
@@ -1029,6 +1026,14 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name,
                            unop(Iop_64to8,cc_dep2)));
       }
 
+      if (isU64(cc_op, AMD64G_CC_OP_SUBB) && isU64(cond, AMD64CondNZ)) {
+         /* byte sub/cmp, then NZ --> test dst!=src */
+         return unop(Iop_1Uto64,
+                     binop(Iop_CmpNE8, 
+                           unop(Iop_64to8,cc_dep1),
+                           unop(Iop_64to8,cc_dep2)));
+      }
+
       if (isU64(cc_op, AMD64G_CC_OP_SUBB) && isU64(cond, AMD64CondS)
                                           && isU64(cc_dep2, 0)) {
          /* byte sub/cmp of zero, then S --> test (dst-0 <s 0)

diff --git a/VEX/priv/guest-x86/ghelpers.c b/VEX/priv/guest-x86/ghelpers.c
index 1db087fada664e1ac36b642f4bcf13c872cdba80..89555342b3f0750e1bdf1853da3ea7a3ab69bdc4 100644 (file)
--- a/VEX/priv/guest-x86/ghelpers.c
+++ b/VEX/priv/guest-x86/ghelpers.c
@@ -1056,6 +1056,16 @@ IRExpr* guest_x86_spechelper ( HChar* function_name,
          return unop(Iop_1Uto32,binop(Iop_CmpLT32S, cc_dep1, mkU32(0)));
       }
 
+      /*---------------- DECW ----------------*/
+
+      if (isU32(cc_op, X86G_CC_OP_DECW) && isU32(cond, X86CondZ)) {
+         /* dec W, then Z --> test dst == 0 */
+         return unop(Iop_1Uto32,
+                     binop(Iop_CmpEQ32, 
+                           binop(Iop_Shl32,cc_dep1,mkU8(16)), 
+                           mkU32(0)));
+      }
+
       /*---------------- INCW ----------------*/
 
       if (isU32(cc_op, X86G_CC_OP_INCW) && isU32(cond, X86CondZ)) {