ASoC: amd: acp: Audio is not resuming after s0ix

[ Upstream commit 3ee257aba1d56c3f0f1028669a8ad0f1a477f05b ]

Audio fails to resume after system exits suspend mode
due to accessing incorrect ring buffer address during
resume. This patch resolves issue by selecting correct
address based on the ACP version.

Fixes: f6f7d25b11033 ("ASoC: amd: acp: Add pte configuration for ACP7.0 platform")
Signed-off-by: Hemalatha Pinnamreddy <hemalatha.pinnamreddy2@amd.com>
Signed-off-by: Raghavendra Prasad Mallela <raghavendraprasad.mallela@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Link: https://patch.msgid.link/20251203064650.2554625-1-raghavendraprasad.mallela@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/amd/acp/acp-legacy-common.c b/sound/soc/amd/acp/acp-legacy-common.c
index 3078f459e0050b2531e261b1c314816d036cbc6d..4e477c48d4bdd1f6ec14434c9e6da62abc3c037f 100644 (file)
--- a/sound/soc/amd/acp/acp-legacy-common.c
+++ b/sound/soc/amd/acp/acp-legacy-common.c
@@ -219,7 +219,10 @@ static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
                                        SP_PB_FIFO_ADDR_OFFSET;
                        reg_fifo_addr = ACP_I2S_TX_FIFOADDR(chip);
                        reg_fifo_size = ACP_I2S_TX_FIFOSIZE(chip);
-                       phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
+                       if (chip->acp_rev >= ACP70_PCI_ID)
+                               phy_addr = ACP7x_I2S_SP_TX_MEM_WINDOW_START;
+                       else
+                               phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
                        writel(phy_addr, chip->base + ACP_I2S_TX_RINGBUFADDR(chip));
                } else {
                        reg_dma_size = ACP_I2S_RX_DMA_SIZE(chip);
@@ -227,7 +230,10 @@ static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
                                        SP_CAPT_FIFO_ADDR_OFFSET;
                        reg_fifo_addr = ACP_I2S_RX_FIFOADDR(chip);
                        reg_fifo_size = ACP_I2S_RX_FIFOSIZE(chip);
-                       phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
+                       if (chip->acp_rev >= ACP70_PCI_ID)
+                               phy_addr = ACP7x_I2S_SP_RX_MEM_WINDOW_START;
+                       else
+                               phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
                        writel(phy_addr, chip->base + ACP_I2S_RX_RINGBUFADDR(chip));
                }
                break;
@@ -238,7 +244,10 @@ static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
                                        BT_PB_FIFO_ADDR_OFFSET;
                        reg_fifo_addr = ACP_BT_TX_FIFOADDR(chip);
                        reg_fifo_size = ACP_BT_TX_FIFOSIZE(chip);
-                       phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
+                       if (chip->acp_rev >= ACP70_PCI_ID)
+                               phy_addr = ACP7x_I2S_BT_TX_MEM_WINDOW_START;
+                       else
+                               phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
                        writel(phy_addr, chip->base + ACP_BT_TX_RINGBUFADDR(chip));
                } else {
                        reg_dma_size = ACP_BT_RX_DMA_SIZE(chip);
@@ -246,7 +255,10 @@ static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
                                        BT_CAPT_FIFO_ADDR_OFFSET;
                        reg_fifo_addr = ACP_BT_RX_FIFOADDR(chip);
                        reg_fifo_size = ACP_BT_RX_FIFOSIZE(chip);
-                       phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
+                       if (chip->acp_rev >= ACP70_PCI_ID)
+                               phy_addr = ACP7x_I2S_BT_RX_MEM_WINDOW_START;
+                       else
+                               phy_addr = I2S_BT_RX_MEM_WINDOW_START + stream->reg_offset;
                        writel(phy_addr, chip->base + ACP_BT_RX_RINGBUFADDR(chip));
                }
                break;
@@ -257,7 +269,10 @@ static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
                                        HS_PB_FIFO_ADDR_OFFSET;
                        reg_fifo_addr = ACP_HS_TX_FIFOADDR;
                        reg_fifo_size = ACP_HS_TX_FIFOSIZE;
-                       phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
+                       if (chip->acp_rev >= ACP70_PCI_ID)
+                               phy_addr = ACP7x_I2S_HS_TX_MEM_WINDOW_START;
+                       else
+                               phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
                        writel(phy_addr, chip->base + ACP_HS_TX_RINGBUFADDR);
                } else {
                        reg_dma_size = ACP_HS_RX_DMA_SIZE;
@@ -265,7 +280,10 @@ static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
                                        HS_CAPT_FIFO_ADDR_OFFSET;
                        reg_fifo_addr = ACP_HS_RX_FIFOADDR;
                        reg_fifo_size = ACP_HS_RX_FIFOSIZE;
-                       phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
+                       if (chip->acp_rev >= ACP70_PCI_ID)
+                               phy_addr = ACP7x_I2S_HS_RX_MEM_WINDOW_START;
+                       else
+                               phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
                        writel(phy_addr, chip->base + ACP_HS_RX_RINGBUFADDR);
                }
                break;