arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY

[ Upstream commit acb94d67f5a23dbb2e0021b6c30609ed05d7d6a5 ]

The USB3 PHY on the QCM2290 platform doesn't have built-in
PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately
via the register in the TCSR space. Declare corresponding register.

Fixes: 0c55f6229bc3 ("arm64: dts: qcom: qcm2290: Add USB3 PHY")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-5-a950c223f10f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index d46e591e72b5c9bb77af2cfbc1b14a43e1664078..40a8506553ef5ddc4f3bb80395f40fffd8de8b9d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -418,6 +418,11 @@
                        #hwlock-cells = <1>;
                };
 
+               tcsr_regs: syscon@3c0000 {
+                       compatible = "qcom,qcm2290-tcsr", "syscon";
+                       reg = <0x0 0x003c0000 0x0 0x40000>;
+               };
+
                tlmm: pinctrl@500000 {
                        compatible = "qcom,qcm2290-tlmm";
                        reg = <0x0 0x00500000 0x0 0x300000>;
@@ -665,6 +670,8 @@
 
                        #phy-cells = <0>;
 
+                       qcom,tcsr-reg = <&tcsr_regs 0xb244>;
+
                        status = "disabled";
                };