RISC-V: Add test cases for RVV FP16 vreinterpret

This patch would like to add more tests for RVV FP16 vreinterpret, aka

vfloat16*_t <==> v{u}int16*_t.

There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already.
It doesn't break anything in SPEC as there is no such vreinterpret insn.
From the user's perspective, it is reasonable to do some type convert
between vfloat16 and v{u}int16 when only ZVFHMIN is enabled.

This patch would like to add new test cases to make sure the RVV FP16
vreinterpret works well as expected.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new cases.
	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Diito.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 2afc105e2da0add24e0ba4c5f53727d86b3a7d85..d5bcdd5156ae595b1274aaa26e3dec4f771ec04f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -29,9 +29,21 @@ vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
   return __riscv_vle16_v_f16m8(base, vl);
 }
 
+vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {
+  return __riscv_vreinterpret_v_i16mf4_f16mf4(src);
+}
+
+vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
+  return __riscv_vreinterpret_v_f16m8_u16m8(src);
+}
+
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 } } */
 /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 3 } } */
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
+/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index f1a29b639e0f6113fb86cae295f3f72b0c14f706..e56b2751d4cad52eaee4a5351d9015ff5dff92b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -53,12 +53,48 @@ vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
   return __riscv_vle16_v_f16m8(base, vl);
 }
 
+vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {
+  return __riscv_vreinterpret_v_i16mf4_f16mf4(src);
+}
+
+vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {
+  return __riscv_vreinterpret_v_i16m8_f16m8(src);
+}
+
+vfloat16mf4_t test_vreinterpret_v_u16mf4_f16mf4(vuint16mf4_t src) {
+  return __riscv_vreinterpret_v_u16mf4_f16mf4(src);
+}
+
+vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {
+  return __riscv_vreinterpret_v_u16m8_f16m8(src);
+}
+
+vint16mf4_t test_vreinterpret_v_f16mf4_i16mf4(vfloat16mf4_t src) {
+  return __riscv_vreinterpret_v_f16mf4_i16mf4(src);
+}
+
+vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {
+  return __riscv_vreinterpret_v_f16m8_i16m8(src);
+}
+
+vuint16mf4_t test_vreinterpret_v_f16mf4_u16mf4(vfloat16mf4_t src) {
+  return __riscv_vreinterpret_v_f16mf4_u16mf4(src);
+}
+
+vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
+  return __riscv_vreinterpret_v_f16m8_u16m8(src);
+}
+
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */
 /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
 /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
+/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 7 } } */
+/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */