aarch64: Use RTL builtins for vq[r]dmulh[q]_n intrinsics

Rewrite vq[r]dmulh[q]_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-08  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Add sq[r]dmulh_n
	builtin generator macros.
	* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_n<mode>):
	Define.
	* config/aarch64/arm_neon.h (vqdmulh_n_s16): Use RTL builtin
	instead of inline asm.
	(vqdmulh_n_s32): Likewise.
	(vqdmulhq_n_s16): Likewise.
	(vqdmulhq_n_s32): Likewise.
	(vqrdmulh_n_s16): Likewise.
	(vqrdmulh_n_s32): Likewise.
	(vqrdmulhq_n_s16): Likewise.
	(vqrdmulhq_n_s32): Likewise.

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index b885bd5b38bf7ad83eb9d801284bf9b34db17210..f79e71682934cb7fa28e01ae7645a083078482f8 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -348,6 +348,9 @@
   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0, NONE)
   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0, NONE)
+  /* Implemented by aarch64_sq<r>dmulh_n<mode>.  */
+  BUILTIN_VDQHS (BINOP, sqdmulh_n, 0, NONE)
+  BUILTIN_VDQHS (BINOP, sqrdmulh_n, 0, NONE)
   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0, NONE)
   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0, NONE)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 4edee99051c4e2112b546becca47da32aae21df2..5245cf01ba3418437583994265bbbd66e89b19d5 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4639,6 +4639,18 @@
   [(set_attr "type" "neon_sat_mul_<Vetype><q>")]
 )
 
+(define_insn "aarch64_sq<r>dmulh_n<mode>"
+  [(set (match_operand:VDQHS 0 "register_operand" "=w")
+       (unspec:VDQHS
+         [(match_operand:VDQHS 1 "register_operand" "w")
+          (vec_duplicate:VDQHS
+            (match_operand:<VEL> 2 "register_operand" "<h_con>"))]
+        VQDMULH))]
+  "TARGET_SIMD"
+  "sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]"
+  [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
+)
+
 ;; sq<r>dmulh_lane
 
 (define_insn "aarch64_sq<r>dmulh_lane<mode>"

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index baa30bd5a9d96c1bf04a37fb105091ea56a6444a..5fb2b3d0d456357cc03445b3a1be75866aae1e29 100644 (file)
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -8769,48 +8769,28 @@ __extension__ extern __inline int16x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqdmulh_n_s16 (int16x4_t __a, int16_t __b)
 {
-  int16x4_t __result;
-  __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]"
-           : "=w"(__result)
-           : "w"(__a), "x"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqdmulh_nv4hi (__a, __b);
 }
 
 __extension__ extern __inline int32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqdmulh_n_s32 (int32x2_t __a, int32_t __b)
 {
-  int32x2_t __result;
-  __asm__ ("sqdmulh %0.2s,%1.2s,%2.s[0]"
-           : "=w"(__result)
-           : "w"(__a), "w"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqdmulh_nv2si (__a, __b);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqdmulhq_n_s16 (int16x8_t __a, int16_t __b)
 {
-  int16x8_t __result;
-  __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
-           : "=w"(__result)
-           : "w"(__a), "x"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqdmulh_nv8hi (__a, __b);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqdmulhq_n_s32 (int32x4_t __a, int32_t __b)
 {
-  int32x4_t __result;
-  __asm__ ("sqdmulh %0.4s,%1.4s,%2.s[0]"
-           : "=w"(__result)
-           : "w"(__a), "w"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqdmulh_nv4si (__a, __b);
 }
 
 __extension__ extern __inline int8x16_t
@@ -8880,48 +8860,28 @@ __extension__ extern __inline int16x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqrdmulh_n_s16 (int16x4_t __a, int16_t __b)
 {
-  int16x4_t __result;
-  __asm__ ("sqrdmulh %0.4h,%1.4h,%2.h[0]"
-           : "=w"(__result)
-           : "w"(__a), "x"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqrdmulh_nv4hi (__a, __b);
 }
 
 __extension__ extern __inline int32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqrdmulh_n_s32 (int32x2_t __a, int32_t __b)
 {
-  int32x2_t __result;
-  __asm__ ("sqrdmulh %0.2s,%1.2s,%2.s[0]"
-           : "=w"(__result)
-           : "w"(__a), "w"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqrdmulh_nv2si (__a, __b);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqrdmulhq_n_s16 (int16x8_t __a, int16_t __b)
 {
-  int16x8_t __result;
-  __asm__ ("sqrdmulh %0.8h,%1.8h,%2.h[0]"
-           : "=w"(__result)
-           : "w"(__a), "x"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqrdmulh_nv8hi (__a, __b);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqrdmulhq_n_s32 (int32x4_t __a, int32_t __b)
 {
-  int32x4_t __result;
-  __asm__ ("sqrdmulh %0.4s,%1.4s,%2.s[0]"
-           : "=w"(__result)
-           : "w"(__a), "w"(__b)
-           : /* No clobbers */);
-  return __result;
+  return __builtin_aarch64_sqrdmulh_nv4si (__a, __b);
 }
 
 __extension__ extern __inline int8x16_t