drm/amdkfd: move SDMA queue reset capability check to node_show

Relocate the per-SDMA queue reset capability check from
kfd_topology_set_capabilities() to node_show() to ensure we read the
latest value of sdma.supported_reset after all IP blocks are initialized.

Fixes: ceb7114c961b ("drm/amdkfd: flag per-sdma queue reset supported to user space")
Reviewed-by: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit e17df7b086cf908cedd919f448da9e00028419bb)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index baa2374acdeb53ada6e52738662df4e86ac1fc80..4ec73f33535ebfc20c9b5dc8c89c52aa4c44b126 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -510,6 +510,10 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
                        dev->node_props.capability |=
                                        HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
 
+               if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0) &&
+                       (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
+                               dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
+
                sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",
                        dev->node_props.max_engine_clk_fcompute);
 
@@ -2008,8 +2012,6 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
                if (!amdgpu_sriov_vf(dev->gpu->adev))
                        dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
 
-               if (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
-                       dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
        } else {
                dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
                                        HSA_DBG_WATCH_ADDR_MASK_HI_BIT;