reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)
/* Handshake with IPU when certain clock rates are changed. */
reg = __raw_readl(&mxc_ccm->ccdr);
reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)
/*
* No handshake with IPU whe dividers are changed
* as its not enabled.
static struct clk ipu_clk = {
.name = "ipu_clk",
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)
.enable_reg =
(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)),
.enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
g_pixel_clk[1] = &pixel_clk[1];
g_ipu_clk = &ipu_clk;
-#if defined(CONFIG_MX51)
+#if CONFIG_IS_ENABLED(MX51)
g_ipu_clk->rate = IPUV3_CLK_MX51;
-#elif defined(CONFIG_MX53)
+#elif CONFIG_IS_ENABLED(MX53)
g_ipu_clk->rate = IPUV3_CLK_MX53;
#else
g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;
#endif
+
debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
g_ldb_clk = &ldb_clk;
debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
#define IPU_DC_REG_BASE 0x00058000
#define IPU_DMFC_REG_BASE 0x00060000
#define IPU_VDI_REG_BASE 0x00680000
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)
#define IPU_CPMEM_REG_BASE 0x01000000
#define IPU_LUT_REG_BASE 0x01020000
#define IPU_SRM_REG_BASE 0x01040000
#define IPU_TPM_REG_BASE 0x01060000
#define IPU_DC_TMPL_REG_BASE 0x01080000
#define IPU_ISP_TBPR_REG_BASE 0x010C0000
-#elif defined(CONFIG_MX6)
+#elif CONFIG_IS_ENABLED(MX6)
#define IPU_CPMEM_REG_BASE 0x00100000
#define IPU_LUT_REG_BASE 0x00120000
#define IPU_SRM_REG_BASE 0x00140000