RISC-V: Add AMO release bits

This patch sets the relevant .rl bits on amo operations.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_print_operand): Change behavior
	of %A to include release bits.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 11af780fc3ee75bf673e3173a6ccf31a86e14d96..f8bc402e35a8899e92d197e26c045eb3e856056d 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4508,8 +4508,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire (model))
+      if (riscv_memmodel_needs_amo_acquire (model)
+         && riscv_memmodel_needs_release_fence (model))
+       fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire (model))
        fputs (".aq", file);
+      else if (riscv_memmodel_needs_release_fence (model))
+       fputs (".rl", file);
       break;
 
     case 'F':