RISC-V: Optimize RVV epilogue logic.

Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.

This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_epilogue):
	Do not emit useless add sp, sp, 0 instrutions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e36ff05695a6a27d2ae803d5007f0fe36acbdc3c..ed8ba833c8ddcdad89a2c6fe5e3588d8880e8d19 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5204,25 +5204,29 @@ riscv_expand_epilogue (int style)
          step1 -= scalable_frame;
        }
 
-      /* Get an rtx for STEP1 that we can add to BASE.  */
-      rtx adjust = GEN_INT (step1.to_constant ());
-      if (!SMALL_OPERAND (step1.to_constant ()))
+      /* Get an rtx for STEP1 that we can add to BASE.
+        Skip if adjust equal to zero.  */
+      if (step1.to_constant () != 0)
        {
-         riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
-         adjust = RISCV_PROLOGUE_TEMP (Pmode);
-       }
-
-      insn = emit_insn (
-              gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
+         rtx adjust = GEN_INT (step1.to_constant ());
+         if (!SMALL_OPERAND (step1.to_constant ()))
+           {
+             riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
+             adjust = RISCV_PROLOGUE_TEMP (Pmode);
+           }
 
-      rtx dwarf = NULL_RTX;
-      rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
-                                        GEN_INT (step2));
+         insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
+                                          stack_pointer_rtx,
+                                          adjust));
+         rtx dwarf = NULL_RTX;
+         rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+                                            GEN_INT (step2));
 
-      dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
-      RTX_FRAME_RELATED_P (insn) = 1;
+         dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+         RTX_FRAME_RELATED_P (insn) = 1;
 
-      REG_NOTES (insn) = dwarf;
+         REG_NOTES (insn) = dwarf;
+       }
     }
   else if (frame_pointer_needed)
     {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644 (file)
index 0000000..f8c9f63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)v; 
+}
+
+/* Make sure we do not have a useless SP adjustment.  */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */