disas: Have disas_set_info() take a const CPUState

The CPUClass::disas_set_info() handler is meant to initialize
the %disassemble_info structure; it shoudn't alter the CPU state.
Enforce the CPUState can not be modified by having the handler
take a const pointer.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260202222412.24923-8-philmd@linaro.org>

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 98678704a64d39c43a5dc9ea83c3e4b7ef968d10..ef20cb356a6a09c9196ba890f409f15a3ddefd48 100644 (file)
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -175,7 +175,7 @@ struct CPUClass {
     const char * (*gdb_arch_name)(CPUState *cpu);
     const char * (*gdb_get_core_xml_file)(CPUState *cpu);
 
-    void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
+    void (*disas_set_info)(const CPUState *cpu, disassemble_info *info);
 
     const char *deprecation_note;
     struct AccelCPUClass *accel_cpu;

diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 932cddac055ce82cc8ad4151a52182ef06ef0859..1780db7d1e297fe7465825cf5c3652b61a0ae222 100644 (file)
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -98,7 +98,8 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
     return alpha_env_mmu_index(cpu_env(cs));
 }
 
-static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void alpha_cpu_disas_set_info(const CPUState *cpu,
+                                     disassemble_info *info)
 {
     info->endian = BFD_ENDIAN_LITTLE;
     info->mach = bfd_mach_alpha_ev6;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 586202071d070ded96ef261a8afdf94c3e676603..c535b292d992931335213b30f33f5818fba7006c 100644 (file)
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -789,10 +789,10 @@ static void arm_wfxt_timer_cb(void *opaque)
 }
 #endif
 
-static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void arm_disas_set_info(const CPUState *cpu, disassemble_info *info)
 {
-    ARMCPU *ac = ARM_CPU(cpu);
-    CPUARMState *env = &ac->env;
+    const ARMCPU *ac = ARM_CPU(cpu);
+    const CPUARMState *env = &ac->env;
     bool sctlr_b = arm_sctlr_b(env);
 
     if (is_a64(env)) {

diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 52237da3ce93613ab9c4c98579e1642dba816022..8579a7283b153b6553d2642c08e34675be2b8d89 100644 (file)
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -116,7 +116,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType type)
     memset(env->r, 0, sizeof(env->r));
 }
 
-static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void avr_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info)
 {
     info->endian = BFD_ENDIAN_LITTLE;
     info->mach = bfd_arch_avr;

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 8ac4f49aa3b09ee1240ae8151a1a77d4cfdf3828..58a22ee41f2564f5f9a331872f5005c1d4a28e1a 100644 (file)
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -301,7 +301,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
     set_float_default_nan_pattern(0b11111111, &env->fp_status);
 }
 
-static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+static void hexagon_cpu_disas_set_info(const CPUState *cs,
+                                       disassemble_info *info)
 {
     info->print_insn = print_insn_hexagon;
     info->endian = BFD_ENDIAN_LITTLE;

diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 0ca79ee5e23a58b8be066070920a1e3250692beb..714f3bbdaf723dd7ead052118b1654155a5230be 100644 (file)
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -150,7 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
     return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX;
 }
 
-static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
+static void hppa_cpu_disas_set_info(const CPUState *cs, disassemble_info *info)
 {
     info->mach = bfd_mach_hppa20;
     info->endian = BFD_ENDIAN_BIG;

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 45f0b80deb022ed70a1ef58c2b68f98f4d1f62b9..0a7b884528eae12f53bc72f8cc8e6b04190acd5d 100644 (file)
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10359,10 +10359,10 @@ static bool x86_cpu_has_work(CPUState *cs)
 }
 #endif /* !CONFIG_USER_ONLY */
 
-static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
+static void x86_disas_set_info(const CPUState *cs, disassemble_info *info)
 {
-    X86CPU *cpu = X86_CPU(cs);
-    CPUX86State *env = &cpu->env;
+    const X86CPU *cpu = X86_CPU(cs);
+    const CPUX86State *env = &cpu->env;
 
     info->endian = BFD_ENDIAN_LITTLE;
     info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b65394852669e2f5b7cc8d287f441f405ca97077..4fa629cb14443fbf719df8fe5942c2089f5762e0 100644 (file)
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -506,7 +506,8 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
     cs->exception_index = -1;
 }
 
-static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+static void loongarch_cpu_disas_set_info(const CPUState *cs,
+                                         disassemble_info *info)
 {
     info->endian = BFD_ENDIAN_LITTLE;
     info->print_insn = print_insn_loongarch;

diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b55e604b11d1651f00abdd2e7159de71060e0e07..c721a23b966803f5494f77ebed3aa9fdb158f77d 100644 (file)
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -176,7 +176,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
     env->pc = 0;
 }
 
-static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+static void m68k_cpu_disas_set_info(const CPUState *cs, disassemble_info *info)
 {
     info->print_insn = print_insn_m68k;
     info->endian = BFD_ENDIAN_BIG;

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 53649ec6567d09bf13af4c7e58bd9eb750712b93..ae41a1a32878dd36c19e743c23c70f88c2bb4e5c 100644 (file)
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -233,7 +233,7 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
 #endif
 }
 
-static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void mb_disas_set_info(const CPUState *cpu, disassemble_info *info)
 {
     info->mach = bfd_arch_microblaze;
     info->print_insn = print_insn_microblaze;

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index f74a9d5f615a77337c9cab25a7c6749085a09722..e424d11501803cc0245012a4fdf953874c1b2482 100644 (file)
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -422,9 +422,12 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
 #endif
 }
 
-static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *info)
 {
-    if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
+    const MIPSCPU *cpu = MIPS_CPU(cs);
+    const CPUMIPSState *env = &cpu->env;
+
+    if (!(env->insn_flags & ISA_NANOMIPS32)) {
         info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
                                          : BFD_ENDIAN_LITTLE;
         info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips

diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 9bbfe22ed3a8549a0c738586807934e33646278d..c64542a59a29b2259ac85515819efb133c6054a8 100644 (file)
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -94,7 +94,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
     return MMU_NOMMU_IDX;  /* mmu is disabled */
 }
 
-static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void openrisc_disas_set_info(const CPUState *cpu, disassemble_info *info)
 {
     info->endian = BFD_ENDIAN_BIG;
     info->print_insn = print_insn_or1k;

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c5cec7c2ed97b9a226c3585acd03507e439c5fd2..c36fd118a998c87779b1c32012f2bd2a15fbd851 100644 (file)
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7452,9 +7452,10 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
     return pcc->pvr == pvr;
 }
 
-static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
+static void ppc_disas_set_info(const CPUState *cs, disassemble_info *info)
 {
-    CPUPPCState *env = cpu_env(cs);
+    const PowerPCCPU *cpu = POWERPC_CPU(cs);
+    const CPUPPCState *env = &cpu->env;
 
     info->endian = ppc_env_is_little_endian(env) ? BFD_ENDIAN_LITTLE
                                                  : BFD_ENDIAN_BIG;

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e95eea024939d2cbb5747781c291fed0e1b07bb9..e56470a37484756b2a3a54886b3f454101d26a38 100644 (file)
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -795,10 +795,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
 #endif
 }
 
-static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info)
 {
-    RISCVCPU *cpu = RISCV_CPU(s);
-    CPURISCVState *env = &cpu->env;
+    const RISCVCPU *cpu = RISCV_CPU(s);
+    const CPURISCVState *env = &cpu->env;
+
     info->target_info = &cpu->cfg;
 
     /*

diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 0437edca1ba2a33b6e14a5d322324b967499cd4d..b5284199e6dce63cd165ddbf5cab598328cf4fa7 100644 (file)
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -178,7 +178,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int request)
     }
 }
 
-static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void rx_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info)
 {
     info->endian = BFD_ENDIAN_LITTLE;
     info->mach = bfd_mach_rx;

diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index cd472d38be7b6977c6fe0569d29f4c90a26af133..c074e12ba2de9d2add8cf800723b82efc06780df 100644 (file)
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -222,7 +222,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
     }
 }
 
-static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void s390_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info)
 {
     info->mach = bfd_mach_s390_64;
     info->cap_arch = CS_ARCH_SYSZ;

diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 1dd21ad9ed6f267e7bda96e3873ce01ebb2146d0..e2bde4576187da350aa5939b250d6d89b832d7c2 100644 (file)
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -164,7 +164,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
     set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
 }
 
-static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void superh_cpu_disas_set_info(const CPUState *cpu,
+                                      disassemble_info *info)
 {
     info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
                                      : BFD_ENDIAN_LITTLE;

diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index bfc6fb9d00d20f61c0aa4d844ae30edc198be1b7..3991681d1d1b7d3cfc572fc048d4929d59247188 100644 (file)
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -103,7 +103,8 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 }
 #endif /* !CONFIG_USER_ONLY */
 
-static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
+static void cpu_sparc_disas_set_info(const CPUState *cpu,
+                                     disassemble_info *info)
 {
     info->print_insn = print_insn_sparc;
     info->endian = BFD_ENDIAN_BIG;

diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index ecc5e093a40ab37d5899697bdb634bfc2125ba9f..86ec899a67ce8a76616e3bd07f572662c3818295 100644 (file)
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -226,7 +226,8 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
-static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
+static void xtensa_cpu_disas_set_info(const CPUState *cs,
+                                      disassemble_info *info)
 {
     XtensaCPU *cpu = XTENSA_CPU(cs);