Select and emit insns for

Iop_ZeroHI64ofV128 Iop_Max8Sx16 Iop_Min8Sx16

git-svn-id: svn://svn.valgrind.org/vex/trunk@2828

diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c
index 1c347680bd78f717cb630f8279e2e09e5175dab5..cae81e1c867cac0bdd00e2b127e329c862bf2532 100644 (file)
--- a/VEX/priv/host_arm64_defs.c
+++ b/VEX/priv/host_arm64_defs.c
@@ -4916,11 +4916,13 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             011 01110 01 1 m  011011 n d   UMIN Vd.8h,  Vn.8h,  Vm.8h
             011 01110 00 1 m  011011 n d   UMIN Vd.16b, Vn.16b, Vm.16b
 
-            010 01110 10 1 m  011001 n d   SMAX Vd.4s, Vn.4s, Vm.4s
-            010 01110 01 1 m  011001 n d   SMAX Vd.8h, Vn.8h, Vm.8h
+            010 01110 10 1 m  011001 n d   SMAX Vd.4s,  Vn.4s,  Vm.4s
+            010 01110 01 1 m  011001 n d   SMAX Vd.8h,  Vn.8h,  Vm.8h
+            010 01110 00 1 m  011001 n d   SMAX Vd.16b, Vn.16b, Vm.16b
 
-            010 01110 10 1 m  011011 n d   SMIN Vd.4s, Vn.4s, Vm.4s
-            010 01110 01 1 m  011011 n d   SMIN Vd.8h, Vn.8h, Vm.8h
+            010 01110 10 1 m  011011 n d   SMIN Vd.4s,  Vn.4s,  Vm.4s
+            010 01110 01 1 m  011011 n d   SMIN Vd.8h,  Vn.8h,  Vm.8h
+            010 01110 00 1 m  011011 n d   SMIN Vd.16b, Vn.16b, Vm.16b
 
             010 01110 00 1 m  000111 n d   AND Vd, Vn, Vm
             010 01110 10 1 m  000111 n d   ORR Vd, Vn, Vm
@@ -5009,6 +5011,9 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             case ARM64vecb_SMAX16x8:
                *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X011001, vN, vD);
                break;
+            case ARM64vecb_SMAX8x16:
+               *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X011001, vN, vD);
+               break;
 
             case ARM64vecb_SMIN32x4:
                *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X011011, vN, vD);
@@ -5016,6 +5021,9 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             case ARM64vecb_SMIN16x8:
                *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X011011, vN, vD);
                break;
+            case ARM64vecb_SMIN8x16:
+               *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X011011, vN, vD);
+               break;
 
             case ARM64vecb_AND:
                *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X000111, vN, vD);
@@ -6005,6 +6013,12 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             *p++ = 0x2F00E5E0 | rQ;
             goto done;
          }
+         if (imm == 0x00FF) {
+            /* movi rD, #0xFFFFFFFFFFFFFFFF == 0x2F 0x07 0xE7 111 rD */
+            vassert(rQ < 32);
+            *p++ = 0x2F07E7E0 | rQ;
+            goto done;
+         }
          goto bad; /* no other handled cases right now */
       }
 

diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
index a17ab75ba30430bbc3a18086fb3ede9e69c7f259..edb37406192eaffc71c54edde2ff22a5d6542769 100644 (file)
--- a/VEX/priv/host_arm64_isel.c
+++ b/VEX/priv/host_arm64_isel.c
@@ -4347,6 +4347,7 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
      /* Iop_ZeroHIXXofV128 cases */
       UShort imm16 = 0;
       switch (e->Iex.Unop.op) {
+         case Iop_ZeroHI64ofV128:  imm16 = 0x00FF; break;
          case Iop_ZeroHI96ofV128:  imm16 = 0x000F; break;
          case Iop_ZeroHI112ofV128: imm16 = 0x0003; break;
          case Iop_ZeroHI120ofV128: imm16 = 0x0001; break;
@@ -4867,8 +4868,10 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
          case Iop_Min8Ux16:
          case Iop_Max32Sx4:
          case Iop_Max16Sx8:
+         case Iop_Max8Sx16:
          case Iop_Min32Sx4:
          case Iop_Min16Sx8:
+         case Iop_Min8Sx16:
          case Iop_Add64x2:
          case Iop_Add32x4:
          case Iop_Add16x8:
@@ -4894,8 +4897,10 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
                case Iop_Min8Ux16:  op = ARM64vecb_UMIN8x16; break;
                case Iop_Max32Sx4:  op = ARM64vecb_SMAX32x4; break;
                case Iop_Max16Sx8:  op = ARM64vecb_SMAX16x8; break;
+               case Iop_Max8Sx16:  op = ARM64vecb_SMAX8x16; break;
                case Iop_Min32Sx4:  op = ARM64vecb_SMIN32x4; break;
                case Iop_Min16Sx8:  op = ARM64vecb_SMIN16x8; break;
+               case Iop_Min8Sx16:  op = ARM64vecb_SMIN8x16; break;
                case Iop_Add64x2:   op = ARM64vecb_ADD64x2; break;
                case Iop_Add32x4:   op = ARM64vecb_ADD32x4; break;
                case Iop_Add16x8:   op = ARM64vecb_ADD16x8; break;