]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1
authorGustavo Sousa <gustavo.sousa@intel.com>
Thu, 14 May 2026 21:44:45 +0000 (18:44 -0300)
committerGustavo Sousa <gustavo.sousa@intel.com>
Fri, 15 May 2026 21:05:12 +0000 (18:05 -0300)
The register COMMON_SLICE_CHICKEN1 is a MCR register on Xe2.
Let's make sure to define a MCR version of it and use it for the
relevant IP versions.

Use XEHP_ as prefix for the register name, since it is MCR as of Xe_HP.

Fixes: a5d221924e13 ("drm/xe/xe2_hpg: Add set of workarounds")
Fixes: 9f18b55b6d3f ("drm/xe/xe2: Add workaround 18033852989")
Bspec: 66534, 71185
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-2-30dd47855fee@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_wa.c

index 408933aee08ad5f5fe41d6c0f3b38729aadec4c8..b21c66a1b777778f019cb5d3d093089663b0ab6b 100644 (file)
 #define   MSAA_OPTIMIZATION_REDUC_DISABLE      REG_BIT(11)
 
 #define COMMON_SLICE_CHICKEN1                  XE_REG(0x7010, XE_REG_OPTION_MASKED)
+#define XEHP_COMMON_SLICE_CHICKEN1             XE_REG_MCR(0x7010, XE_REG_OPTION_MASKED)
 #define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST   REG_BIT(14)
 
 #define HIZ_CHICKEN                                    XE_REG(0x7018, XE_REG_OPTION_MASKED)
index 49f5e3e4c7cc1e08101b4adb1ec3b3cf4c3227c1..d6f94486673e5d432e3f3cf4c14d054dd2264dd8 100644 (file)
@@ -664,7 +664,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
        },
        { XE_RTP_NAME("18033852989"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
+         XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
        },
        { XE_RTP_NAME("15016589081"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),