backport: re PR rtl-optimization/51374 ([avr] insn combine reorders volatile memory...

gcc/
	Backport from mainline r183796
	PR rtl-optimization/51374
	* combine.c (can_combine_p): Don't allow volatile_refs_p insns
	to cross other volatile_refs_p insns.

gcc/testsuite/
	Backport from mainline r183796
	PR rtl-optimization/51374
	* testsuite/gcc.target/avr/torture/pr51374-1.c: New.

From-SVN: r183797

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 02e2c74f5470593a37fe89d0ab9659f3035fecdc..f2816c4caaa81b10858f43a9eb04f6f0cf16eef8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2012-01-12  Georg-Johann Lay  <avr@gjlay.de>
+
+       Backport from mainline r183796
+       PR rtl-optimization/51374
+       * combine.c (can_combine_p): Don't allow volatile_refs_p insns
+       to cross other volatile_refs_p insns.
+
 2012-01-31  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
        Backport from mainline.

diff --git a/gcc/combine.c b/gcc/combine.c
index 0ffd284ca99e8ef6f5478af076403dc988d57489..5980fcbbb03af82856268e8ae7953a38110bde6a 100644 (file)
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1666,6 +1666,7 @@ can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
   rtx link;
 #endif
   bool all_adjacent = true;
+  int (*is_volatile_p) (const_rtx);
 
   if (succ)
     {
@@ -1914,11 +1915,17 @@ can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
     return 0;
 
-  /* If there are any volatile insns between INSN and I3, reject, because
-     they might affect machine state.  */
+  /* If INSN contains volatile references (specifically volatile MEMs),
+     we cannot combine across any other volatile references.
+     Even if INSN doesn't contain volatile references, any intervening
+     volatile insn might affect machine state.  */
 
+  is_volatile_p = volatile_refs_p (PATTERN (insn))
+    ? volatile_refs_p
+    : volatile_insn_p;
+    
   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
-    if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
+    if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
       return 0;
 
   /* If INSN contains an autoincrement or autodecrement, make sure that

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ae16f720eb7bbd7ae8d2e9a7a8b790e33c72b311..1d2e16516183ecf7dc5ce2166a4476f9a3385691 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2012-01-12  Georg-Johann Lay  <avr@gjlay.de>
+
+       Backport from mainline r183796
+       PR rtl-optimization/51374
+       * testsuite/gcc.target/avr/torture/pr51374-1.c: New.
+
 2012-01-30  Bin Cheng  <bin.cheng@arm.com>
 
        Backport from mainline.

diff --git a/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c b/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c
new file mode 100644 (file)
index 0000000..9c98ea5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c
@@ -0,0 +1,15 @@
+/* PR rtl-optimization/51374 */
+/* { dg-do compile } */
+
+void vector_18 (void)
+{
+    extern char slot;
+    unsigned char status = (*(volatile unsigned char*) 0x2B);
+    unsigned char data   = (*(volatile unsigned char*) 0x2C);
+
+    if (status & 0x10)
+        slot = 0;
+}
+
+/* { dg-final { scan-assembler-not "\tsbic " } } */
+/* { dg-final { scan-assembler-not "\tsbis " } } */