]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: mac: update WP quota for RTL8922D
authorPing-Ke Shih <pkshih@realtek.com>
Thu, 8 Jan 2026 12:03:15 +0000 (20:03 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Tue, 13 Jan 2026 02:27:40 +0000 (10:27 +0800)
WP (WiFi payload) quota is to point to payload being transmitting in
memory. Assign quota to indicate WP page full.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260108120320.2217402-9-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/mac_be.c
drivers/net/wireless/realtek/rtw89/reg.h

index 0877cb342b942e99acf467cbee47c02fef6c2ee1..c008931ccb0591b02f3ec2eb2bd3b37cc7c1cf45 100644 (file)
@@ -4000,6 +4000,11 @@ struct rtw89_hfc_prec_cfg {
        u8 h2c_full_cond;
        u8 wp_ch07_full_cond;
        u8 wp_ch811_full_cond;
+       /* for WiFi 7 chips after 8922D */
+       u16 ch011_full_page;
+       u16 h2c_full_page;
+       u16 wp_ch07_full_page;
+       u16 wp_ch811_full_page;
 };
 
 struct rtw89_hfc_param {
index 35794488a02f8697b51c075dd3fdf6623029c66f..a008a1a02fe9a0ca67b4ec75daeb2fabe523c586 100644 (file)
@@ -1701,8 +1701,8 @@ static int sys_init_ax(struct rtw89_dev *rtwdev)
 
 const struct rtw89_mac_size_set rtw89_mac_size = {
        .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0},
-       .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0},
-       .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0},
+       .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0, 2, 32, 0, 0},
+       .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0, 0, 256, 0, 0},
        /* PCIE 64 */
        .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
        .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,},
index 0327629d2a5d3d591cbab41d45853f6d46bf3f16..5df243cf448e67e38f17d550da08bf433fa0e472 100644 (file)
@@ -89,6 +89,7 @@ static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev)
        struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;
        struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;
        struct rtw89_hfc_pub_info *info = &param->pub_info;
+       const struct rtw89_chip_info *chip = rtwdev->chip;
        u32 val;
 
        val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1);
@@ -116,14 +117,23 @@ static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev)
 
        val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL);
        prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);
+       if (chip->chip_id == RTL8922D)
+               prec_cfg->ch011_full_page = u32_get_bits(val, B_BE_FULL_WD_PG_MASK);
        prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);
 
        val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2);
        pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);
 
        val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1);
-       prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
-       prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
+       if (chip->chip_id == RTL8922D) {
+               prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_V1_MASK);
+               prec_cfg->wp_ch07_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH07_MASK);
+               prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_V1_MASK);
+               prec_cfg->wp_ch811_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH811_MASK);
+       } else {
+               prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
+               prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
+       }
 
        val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2);
        pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);
@@ -148,17 +158,26 @@ static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev)
        struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
        const struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;
        const struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;
+       const struct rtw89_chip_info *chip = rtwdev->chip;
        u32 val;
 
        val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |
              u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
+       if (chip->chip_id == RTL8922D)
+               val = u32_replace_bits(val, prec_cfg->ch011_full_page, B_BE_FULL_WD_PG_MASK);
        rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
 
        val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);
        rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val);
 
-       val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
-             u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
+       if (chip->chip_id == RTL8922D)
+               val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_V1_MASK) |
+                     u32_encode_bits(prec_cfg->wp_ch07_full_page, B_BE_FULL_PAGE_WP_CH07_MASK) |
+                     u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_V1_MASK) |
+                     u32_encode_bits(prec_cfg->wp_ch811_full_page, B_BE_FULL_PAGE_WP_CH811_MASK);
+       else
+               val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
+                     u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
        rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val);
 
        val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL),
index e41a6c679d592b2a7c4dc21ee3411483d5a1f015..79c976c25de51ed468b82e3eacf114dbb8b9d65d 100644 (file)
 
 #define R_BE_CH_PAGE_CTRL 0xB704
 #define B_BE_PREC_PAGE_CH12_V1_MASK GENMASK(21, 16)
+#define B_BE_FULL_WD_PG_MASK GENMASK(15, 8)
 #define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0)
 
 #define R_BE_CH0_PAGE_CTRL 0xB718
 #define R_BE_WP_PAGE_CTRL1 0xB7A4
 #define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
 #define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
+#define B_BE_FULL_PAGE_WP_CH811_MASK GENMASK(31, 24)
+#define B_BE_PREC_PAGE_WP_CH811_V1_MASK GENMASK(23, 16)
+#define B_BE_FULL_PAGE_WP_CH07_MASK GENMASK(15, 8)
+#define B_BE_PREC_PAGE_WP_CH07_V1_MASK GENMASK(7, 0)
 
 #define R_BE_WP_PAGE_CTRL2 0xB7A8
 #define B_BE_WP_THRD_MASK GENMASK(12, 0)