clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114

The CSUS clock is a clock gate for the output clock signal primarily
sourced from the VI_SENSOR clock. This clock signal is used as an input
MCLK clock for cameras.

Unlike later Tegra SoCs, the Tegra 20 can change its CSUS parent, which is
why csus_mux is added in a similar way to how CDEV1 and CDEV2 are handled.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 6c8e053311c35ecd7d9bac1cf0248a3887cbb7fb..a4f40533cc435008573f86d7446235f24734277c 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -690,7 +690,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
        [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
        [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
        [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
-       [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
        [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
        [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
        [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
@@ -1046,6 +1045,12 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
                                             0, 82, periph_clk_enb_refcnt);
        clks[TEGRA114_CLK_DSIB] = clk;
 
+       /* csus */
+       clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
+                                            clk_base, 0, TEGRA114_CLK_CSUS,
+                                            periph_clk_enb_refcnt);
+       clks[TEGRA114_CLK_CSUS] = clk;
+
        /* emc mux */
        clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
                               ARRAY_SIZE(mux_pllmcp_clkm),

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index c606c2b160d642a66db3180970b9d600086a5dfd..9da82dd7965ba7d5c819eb18c8bf6237fdf03910 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -530,7 +530,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
        [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
        [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
        [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
-       [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
        [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
        [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
        [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
@@ -834,6 +833,12 @@ static void __init tegra20_periph_clk_init(void)
                                    clk_base, 0, 93, periph_clk_enb_refcnt);
        clks[TEGRA20_CLK_CDEV2] = clk;
 
+       /* csus */
+       clk = tegra_clk_register_periph_gate("csus", "csus_mux", 0,
+                                            clk_base, 0, TEGRA20_CLK_CSUS,
+                                            periph_clk_enb_refcnt);
+       clks[TEGRA20_CLK_CSUS] = clk;
+
        for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
                data = &tegra_periph_clk_list[i];
                clk = tegra_clk_register_periph_data(clk_base, data);
@@ -1093,14 +1098,15 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
        hw = __clk_get_hw(clk);
 
        /*
-        * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
-        * clock is created by the pinctrl driver. It is possible for clk user
-        * to request these clocks before pinctrl driver got probed and hence
-        * user will get an orphaned clock. That might be undesirable because
-        * user may expect parent clock to be enabled by the child.
+        * Tegra20 CDEV1, CDEV2 and CSUS clocks are a bit special case, their
+        * parent clock is created by the pinctrl driver. It is possible for
+        * clk user to request these clocks before pinctrl driver got probed
+        * and hence user will get an orphaned clock. That might be undesirable
+        * because user may expect parent clock to be enabled by the child.
         */
        if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
-           clkspec->args[0] == TEGRA20_CLK_CDEV2) {
+           clkspec->args[0] == TEGRA20_CLK_CDEV2 ||
+           clkspec->args[0] == TEGRA20_CLK_CSUS) {
                parent_hw = clk_hw_get_parent(hw);
                if (!parent_hw)
                        return ERR_PTR(-EPROBE_DEFER);

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e7ebb63970d337fc58c4878e64f1c618dc86de1b..ca738bc64615e1382b4f11230306a2578eb6fb79 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -780,7 +780,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
        [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
        [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
        [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
-       [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
        [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
        [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
        [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
@@ -1009,6 +1008,12 @@ static void __init tegra30_periph_clk_init(void)
                                    0, 48, periph_clk_enb_refcnt);
        clks[TEGRA30_CLK_DSIA] = clk;
 
+       /* csus */
+       clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
+                                            clk_base, 0, TEGRA30_CLK_CSUS,
+                                            periph_clk_enb_refcnt);
+       clks[TEGRA30_CLK_CSUS] = clk;
+
        /* pcie */
        clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
                                    70, periph_clk_enb_refcnt);