Allow "sub.w reg, sp, reg, lsl #N" for N in 0 .. 5 rather than N in 0 .. 3.

Fixes bug 379890.  (jeundery@gmail.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@3379

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index e3a7e1eff858d591a76e92d80b4483f3c5dbc237..b26393ac8e27d620296fb0aabd52196bce66835d 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -21153,10 +21153,10 @@ DisResult disInstr_THUMB_WRK (
           && rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
          valid = True;
       }
-      /* also allow "sub.w reg, sp, reg   lsl #N for N=0,1,2 or 3
+      /* also allow "sub.w reg, sp, reg   lsl #N for N=0 .. 5
          (T1) "SUB (SP minus register) */
       if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
-          && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
+          && rD != 15 && rN == 13 && imm5 <= 5 && how == 0) {
          valid = True;
       }
       if (valid) {