]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/amdgpu: Check vcn sram load return value
authorSathishkumar S <sathishkumar.sundararaju@amd.com>
Sat, 12 Jul 2025 19:58:02 +0000 (01:28 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 13 Nov 2025 20:34:09 +0000 (15:34 -0500)
[ Upstream commit faab5ea0836733ef1c8e83cf6b05690a5c9066be ]

Log an error when vcn sram load fails in indirect mode
and return the same error value.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

index f0edaabdcde5d0719211ae229a39d0b0b8bab953..f085fdaafae00afb9d7cc8d35154aa8f6bd0cc66 100644 (file)
@@ -842,6 +842,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
        volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
        struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
        uint32_t rb_bufsz, tmp;
+       int ret;
 
        vcn_v2_0_enable_static_power_gating(adev);
 
@@ -925,8 +926,13 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
                UVD, 0, mmUVD_MASTINT_EN),
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, 0, 0);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, 0, 0);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        /* force RBC into idle state */
        rb_bufsz = order_base_2(ring->ring_size);
index e4d0c0310e76d4d12931753113931a66fd83f172..274d5063e9a2654178fef52392be31a3e9e8cc7e 100644 (file)
@@ -870,6 +870,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
        volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        uint32_t rb_bufsz, tmp;
+       int ret;
 
        /* disable register anti-hang mechanism */
        WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
@@ -960,8 +961,13 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
                VCN, 0, mmUVD_MASTINT_EN),
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        ring = &adev->vcn.inst[inst_idx].ring_dec;
        /* force RBC into idle state */
index 970041452096357856c8be2adb71dce744350d51..4196bdece253b6ba12437ff92980611abe8981a0 100644 (file)
@@ -990,6 +990,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
        volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        uint32_t rb_bufsz, tmp;
+       int ret;
 
        /* disable register anti-hang mechanism */
        WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
@@ -1082,8 +1083,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
                VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        ring = &adev->vcn.inst[inst_idx].ring_dec;
        /* force RBC into idle state */
index 33d413444a46ac55ff4962b9f6e0da29aec138b5..ae510fd9d29442b4e71b57170948d4f88695103b 100644 (file)
@@ -963,6 +963,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
        volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        uint32_t tmp;
+       int ret;
 
        /* disable register anti-hang mechanism */
        WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@@ -1045,8 +1046,13 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
index 77542dabec59f47c01564ad0b49a6aa19e537a73..2094357a931c440bee30a42be52b6a261063c3dd 100644 (file)
@@ -778,7 +778,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
        volatile struct amdgpu_vcn4_fw_shared *fw_shared =
                                                adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
-       int vcn_inst;
+       int vcn_inst, ret;
        uint32_t tmp;
 
        vcn_inst = GET_INST(VCN, inst_idx);
@@ -871,8 +871,13 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
                VCN, 0, regUVD_MASTINT_EN),
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
index 3d114ea7049f7cd15bf4186c47e2522d0f14aaf6..48cb61a9c13fe0a37ee0132926f6d05f5bb80da2 100644 (file)
@@ -876,6 +876,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
        volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        uint32_t tmp;
+       int ret;
 
        /* disable register anti-hang mechanism */
        WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@@ -956,8 +957,13 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
                VCN, inst_idx, regUVD_MASTINT_EN),
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
index d19eec4d4790508051bb32f77128e5d96077e7b2..cc7add217fd19ba9a22de7e53757d7cb8117f84c 100644 (file)
@@ -665,6 +665,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
        volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        uint32_t tmp;
+       int ret;
 
        /* disable register anti-hang mechanism */
        WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@@ -718,8 +719,12 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
                VCN, inst_idx, regUVD_MASTINT_EN),
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
+               dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret);
+               if (ret)
+                       return ret;
+       }
 
        ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
index cdefd7fcb0da607d36e947c1eefe01c5dc71abdb..d8bbb937673180c74b047f9a56388516687b8afc 100644 (file)
@@ -605,7 +605,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
                adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE};
-       int vcn_inst;
+       int vcn_inst, ret;
        uint32_t tmp;
 
        vcn_inst = GET_INST(VCN, inst_idx);
@@ -666,8 +666,13 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
                VCN, 0, regUVD_MASTINT_EN),
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
-       if (indirect)
-               amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
+       if (indirect) {
+               ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
+               if (ret) {
+                       dev_err(adev->dev, "vcn sram load failed %d\n", ret);
+                       return ret;
+               }
+       }
 
        /* resetting ring, fw should not check RB ring */
        fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;