]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: qcom: glymur: fix QUP serial engine IRQs
authorBjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Thu, 11 Jun 2026 17:22:37 +0000 (17:22 +0000)
committerBjorn Andersson <andersson@kernel.org>
Mon, 29 Jun 2026 01:02:17 +0000 (20:02 -0500)
The Geni serial-engine interrupts from QUP wrapper 0 all fall in ESPI
INTIDs space. While some of the i2c instances has gotten their
interrupt specifiers corrected, even the other functions on the same
serial-engines are wrong.

Ensure that all the serial engine interrupts for QUP wrapper 0 matches
the datasheet.

Assisted-by: Codex:GPT-5.5
Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260611-glymur-geni-irqs-v1-1-269428faeb6d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/glymur.dtsi

index c7edfa8156f3afe3d31dc8e3f2c41669ead8f28b..129be417ac42457e76d02f97935ba94f49b26cb9 100644 (file)
                        spi0: spi@b80000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b80000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        i2c1: i2c@b84000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0x0 0x00b84000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi1: spi@b84000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b84000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        i2c2: i2c@b88000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0x0 0x00b88000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi2: spi@b88000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b88000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        uart2: serial@b88000 {
                                compatible = "qcom,geni-uart";
                                reg = <0x0 0x00b88000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi3: spi@b8c000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b8c000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi4: spi@b90000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b90000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi5: spi@b94000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b94000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        i2c6: i2c@b98000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0x0 0x00b98000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi6: spi@b98000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b98000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        i2c7: i2c@b9c000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0x0 0x00b9c000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
                        spi7: spi@b9c000 {
                                compatible = "qcom,geni-spi";
                                reg = <0x0 0x00b9c000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
                                clock-names = "se";
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS