RISC-V: Delete obsolete MIPS comment.

	gcc/
	* config/riscv/riscv.h (FUNCTION_ARG_REGNO_P): Fix comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@264652 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e134f91d2ba96c7412aa0f118c223ea8b7216f6e..49ff24ccca7123af11c7febc64d1dd8c55e046bd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2018-09-26  Jim Wilson  <jimw@sifive.com>
+
+       * config/riscv/riscv.h (FUNCTION_ARG_REGNO_P): Fix comment.
+
 2018-09-26  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/87414

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4bbb491ac87f49a6d02a8e300233f7c2d06eafce..3c9f96d6b4df9980b909a30163d1b2a6de11f006 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -516,8 +516,7 @@ enum reg_class
 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 
 /* 1 if N is a possible register number for function argument passing.
-   We have no FP argument registers when soft-float.  When FP registers
-   are 32 bits, we can't directly reference the odd numbered ones.  */
+   We have no FP argument registers when soft-float.  */
 
 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 #define FUNCTION_ARG_REGNO_P(N)                                                \