]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
crypto: qat - fix indentation of macros in qat_hal.c
authorSuman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Tue, 5 May 2026 10:17:37 +0000 (06:17 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 14 May 2026 13:31:19 +0000 (15:31 +0200)
[ Upstream commit 4963b39e3a3feed07fbf4d5cc2b5df8498888285 ]

The macros in qat_hal.c were using a mixture of tabs and spaces.
Update all macro indentation to use tabs consistently, matching the
predominant style.

This does not introduce any functional change.

Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Stable-dep-of: e7dcb722bb75 ("crypto: qat - fix firmware loading failure for GEN6 devices")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/crypto/intel/qat/qat_common/qat_hal.c

index 7a6ba6f22e3e8ecc651dfe7fae00d75d132d0589..0f5a2690690a1e48132f90cc81b7fa59c4978249 100644 (file)
@@ -9,17 +9,17 @@
 #include "icp_qat_hal.h"
 #include "icp_qat_uclo.h"
 
-#define BAD_REGADDR           0xffff
-#define MAX_RETRY_TIMES           10000
-#define INIT_CTX_ARB_VALUE     0x0
-#define INIT_CTX_ENABLE_VALUE     0x0
-#define INIT_PC_VALUE       0x0
-#define INIT_WAKEUP_EVENTS_VALUE  0x1
-#define INIT_SIG_EVENTS_VALUE     0x1
-#define INIT_CCENABLE_VALUE       0x2000
-#define RST_CSR_QAT_LSB           20
-#define RST_CSR_AE_LSB           0
-#define MC_TIMESTAMP_ENABLE       (0x1 << 7)
+#define BAD_REGADDR                    0xffff
+#define MAX_RETRY_TIMES                        10000
+#define INIT_CTX_ARB_VALUE             0x0
+#define INIT_CTX_ENABLE_VALUE          0x0
+#define INIT_PC_VALUE                  0x0
+#define INIT_WAKEUP_EVENTS_VALUE       0x1
+#define INIT_SIG_EVENTS_VALUE          0x1
+#define INIT_CCENABLE_VALUE            0x2000
+#define RST_CSR_QAT_LSB                        20
+#define RST_CSR_AE_LSB                 0
+#define MC_TIMESTAMP_ENABLE            (0x1 << 7)
 
 #define IGNORE_W1C_MASK ((~(1 << CE_BREAKPOINT_BITPOS)) & \
        (~(1 << CE_CNTL_STORE_PARITY_ERROR_BITPOS)) & \