re PR target/48090 (gcc 4.5.2 miscompilation when building on arm)

Fix PR target/48090

From-SVN: r172320

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 83e48e59671b017cf4c1b43b23569da7b0de5a40..fdd2535499ff7fa1db59106b78497021deae90a1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-04-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+       Backport from mainline:
+       2011-04-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+       PR target/48090
+       * config/arm/arm.md (*arm_negdi2): Fix early clobber constraints.
+
 2011-04-12  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        Backport from mainline:

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 0de4a1441d5ac3a445d7074ff9cf8d0be97a6bab..8a957d71c7a9dfe3b4a9ba480f7b7324f94e24ca 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3554,7 +3554,7 @@
 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
 ;; The first alternative allows the common case of a *full* overlap.
 (define_insn "*arm_negdi2"
-  [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
+  [(set (match_operand:DI         0 "s_register_operand" "=r,&r")
        (neg:DI (match_operand:DI 1 "s_register_operand"  "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"