Update the Intel PMC Core driver to fetch PMC information only for
available PMCs. Previously, the driver attempted to retrieve PMC info
even when the corresponding PMC was not present.
This change aligns with recent updates to the Intel SSRAM Telemetry
driver. Starting with NVL, the SSRAM Telemetry driver is probed for
each individual SSRAM device. The prior implementation could not
differentiate between an unavailable PMC and one that had not yet
completed information retrieval. To resolve this, the PMC Core driver
now skips obtaining PMC info for unavailable PMCs.
Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
Link: https://patch.msgid.link/20260505043342.2573556-7-xi.pardee@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
{}
};
+static const u8 arl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_PCH};
+static const u8 arl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE};
+
#define ARL_NPU_PCI_DEV 0xad1d
#define ARL_GNA_PCI_DEV 0xae4c
#define ARL_H_NPU_PCI_DEV 0x7d1d
static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
struct pmc_dev_info arl_pmc_dev = {
.dmu_guids = ARL_PMT_DMU_GUIDS,
+ .num_pmcs = ARRAY_SIZE(arl_pmc_list),
+ .pmc_list = arl_pmc_list,
.regmap_list = arl_pmc_info_list,
.map = &arl_socs_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
struct pmc_dev_info arl_h_pmc_dev = {
.dmu_guids = ARL_H_PMT_DMU_GUIDS,
+ .num_pmcs = ARRAY_SIZE(arl_h_pmc_list),
+ .pmc_list = arl_h_pmc_list,
.regmap_list = arl_pmc_info_list,
.map = &mtl_socm_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
return 0;
}
-static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev)
+static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev, u8 num_pmcs, const u8 *pmc_list)
{
+ unsigned int i;
int ret;
- ret = pmc_core_pmc_add(pmcdev, PMC_IDX_MAIN);
- if (ret)
- return ret;
-
- pmc_core_pmc_add(pmcdev, PMC_IDX_IOE);
- pmc_core_pmc_add(pmcdev, PMC_IDX_PCH);
+ for (i = 0; i < num_pmcs; ++i) {
+ /* Non-MAIN PMCs are allowed to fail */
+ ret = pmc_core_pmc_add(pmcdev, pmc_list[i]);
+ if (ret && (pmc_list[i] == PMC_IDX_MAIN))
+ return ret;
+ }
return 0;
}
ssram = pmc_dev_info->regmap_list != NULL;
if (ssram) {
pmcdev->regmap_list = pmc_dev_info->regmap_list;
- ret = pmc_core_ssram_get_reg_base(pmcdev);
+ ret = pmc_core_ssram_get_reg_base(pmcdev,
+ pmc_dev_info->num_pmcs,
+ pmc_dev_info->pmc_list);
/*
* EAGAIN error code indicates Intel PMC SSRAM Telemetry driver
* has not finished probe and PMC info is not available yet. Try
* @pc_guid: GUID for telemetry region to read PKGC blocker info
* @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
* @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
+ * @num_pmcs: Number of entries in @pmc_list
+ * @pmc_list: Index list of available PMC
* @regmap_list: Pointer to a list of pmc_info structure that could be
* available for the platform. When set, this field implies
* SSRAM support.
u32 pc_guid;
u32 pkgc_ltr_blocker_offset;
u32 pkgc_blocker_offset;
+ u8 num_pmcs;
+ const u8 *pmc_list;
struct pmc_info *regmap_list;
const struct pmc_reg_map *map;
const struct file_operations *sub_req_show;
{}
};
+static const u8 lnl_pmc_list[] = {PMC_IDX_MAIN};
+
#define LNL_NPU_PCI_DEV 0x643e
#define LNL_IPU_PCI_DEV 0x645d
}
struct pmc_dev_info lnl_pmc_dev = {
+ .num_pmcs = ARRAY_SIZE(lnl_pmc_list),
+ .pmc_list = lnl_pmc_list,
.regmap_list = lnl_pmc_info_list,
.map = &lnl_socm_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
{}
};
+static const u8 mtl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE};
+
#define MTL_GNA_PCI_DEV 0x7e4c
#define MTL_IPU_PCI_DEV 0x7d19
#define MTL_VPU_PCI_DEV 0x7d1d
static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0};
struct pmc_dev_info mtl_pmc_dev = {
.dmu_guids = MTL_PMT_DMU_GUIDS,
+ .num_pmcs = ARRAY_SIZE(mtl_pmc_list),
+ .pmc_list = mtl_pmc_list,
.regmap_list = mtl_pmc_info_list,
.map = &mtl_socm_reg_map,
.sub_req_show = &pmc_core_substate_req_regs_fops,
{}
};
+static const u8 ptl_pmc_list[] = {PMC_IDX_MAIN};
+
#define PTL_NPU_PCI_DEV 0xb03e
#define PTL_IPU_PCI_DEV 0xb05d
}
struct pmc_dev_info ptl_pmc_dev = {
+ .num_pmcs = ARRAY_SIZE(ptl_pmc_list),
+ .pmc_list = ptl_pmc_list,
.regmap_list = ptl_pmc_info_list,
.map = &ptl_pcdp_reg_map,
.sub_req_show = &pmc_core_substate_blk_req_fops,
{}
};
+static const u8 wcl_pmc_list[] = {PMC_IDX_MAIN};
+
#define WCL_NPU_PCI_DEV 0xfd3e
/*
struct pmc_dev_info wcl_pmc_dev = {
.regmap_list = wcl_pmc_info_list,
+ .num_pmcs = ARRAY_SIZE(wcl_pmc_list),
+ .pmc_list = wcl_pmc_list,
.map = &wcl_pcdn_reg_map,
.sub_req_show = &pmc_core_substate_blk_req_fops,
.suspend = cnl_suspend,