mmc: host: renesas_sdhi: Fix the actual clock

[ Upstream commit 9c174e4dacee9fb2014a4ffc953d79a5707b77e4 ]

Wrong actual clock reported, if the SD clock division ratio is other
than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111).

On high speed mode, cat /sys/kernel/debug/mmc1/ios
Without the patch:
clock:          50000000 Hz
actual clock:   200000000 Hz

After the fix:
clock:          50000000 Hz
actual clock:   50000000 Hz

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250629203859.170850-1-biju.das.jz@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 23fd93407ecedce755ea562aa18fbb8b9e9384b1..0a79b718cf17c2c69b5a427d0114747ab703cbbe 100644 (file)
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -185,7 +185,11 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
                        clk &= ~0xff;
        }
 
-       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
+       clock = clk & CLK_CTL_DIV_MASK;
+       if (clock != 0xff)
+               host->mmc->actual_clock /= (1 << (ffs(clock) + 1));
+
+       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock);
        if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
                usleep_range(10000, 11000);