drm/amdgpu: Enable support for PSP 15_0_5

Add PSP 15.0.5 related offsets for GFX to KMD interface
and enable support for it.

Co-developed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit b01e244c82c5d033d7424a64abe4079f3fceb869)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 2860f12915c02a5bae524ab3b2700a979ebaab4b..5e83edbd313b38bfcff243b9b9972ba3ef8a3660 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2304,6 +2304,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
                amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
                break;
        case IP_VERSION(15, 0, 0):
+       case IP_VERSION(15, 0, 5):
        case IP_VERSION(15, 0, 9):
                amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block);
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index ca80b6194cac1c99c56474d4d6998bd92b4dd0ff..7139cb3b2db5b3849e4aa2d5f7cddcc1a4395830 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -275,6 +275,7 @@ static int psp_early_init(struct amdgpu_ip_block *ip_block)
                psp->boot_time_tmr = false;
                break;
        case IP_VERSION(15, 0, 0):
+       case IP_VERSION(15, 0, 5):
        case IP_VERSION(15, 0, 9):
                psp_v15_0_0_set_psp_funcs(psp);
                psp->boot_time_tmr = false;
@@ -3503,8 +3504,10 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
                     amdgpu_ip_version(adev, MP0_HWIP, 0) ==
                             IP_VERSION(15, 0, 0) ||
                     amdgpu_ip_version(adev, MP0_HWIP, 0) ==
-                            IP_VERSION(15, 0, 8) ||
+                            IP_VERSION(15, 0, 5) ||
                     amdgpu_ip_version(adev, MP0_HWIP, 0) ==
+                            IP_VERSION(15, 0, 8) ||
+                       amdgpu_ip_version(adev, MP0_HWIP, 0) ==
                             IP_VERSION(15, 0, 9)) &&
                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
                     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
index 2a4d91368ac6007dc2cc057c541c238955a723b3..abaa40b6def90dcc5e7c64749c3d194d887e3904 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
@@ -33,9 +33,22 @@
 
 MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin");
 MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_15_0_5_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_15_0_5_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc.bin");
 MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta.bin");
 
+#define regMPASP_PCRU0_MPASP_C2PMSG_64                                         0x4280
+#define regMPASP_PCRU0_MPASP_C2PMSG_64_BASE_IDX                                2
+#define regMPASP_PCRU0_MPASP_C2PMSG_67                                         0x4283
+#define regMPASP_PCRU0_MPASP_C2PMSG_67_BASE_IDX                                2
+#define regMPASP_PCRU0_MPASP_C2PMSG_69                                         0x4285
+#define regMPASP_PCRU0_MPASP_C2PMSG_69_BASE_IDX                                2
+#define regMPASP_PCRU0_MPASP_C2PMSG_70                                         0x4286
+#define regMPASP_PCRU0_MPASP_C2PMSG_70_BASE_IDX                                2
+#define regMPASP_PCRU0_MPASP_C2PMSG_71                                         0x4287
+#define regMPASP_PCRU0_MPASP_C2PMSG_71_BASE_IDX                                2
+
 static int psp_v15_0_0_init_microcode(struct psp_context *psp)
 {
        struct amdgpu_device *adev = psp->adev;
@@ -71,14 +84,25 @@ static int psp_v15_0_0_ring_stop(struct psp_context *psp,
                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
                                   0x80000000, 0x80000000, false);
        } else {
-               /* Write the ring destroy command*/
-               WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
-                            GFX_CTRL_CMD_ID_DESTROY_RINGS);
-               /* there might be handshake issue with hardware which needs delay */
-               mdelay(20);
-               /* Wait for response flag (bit 31) */
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
-                                  0x80000000, 0x80000000, false);
+               if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) {
+                               /* Write the ring destroy command*/
+                       WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64,
+                                       GFX_CTRL_CMD_ID_DESTROY_RINGS);
+                       /* there might be handshake issue with hardware which needs delay */
+                       mdelay(20);
+                       /* Wait for response flag (bit 31) */
+                       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64),
+                                       0x80000000, 0x80000000, false);
+                       } else {
+                               /* Write the ring destroy command*/
+                               WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
+                                               GFX_CTRL_CMD_ID_DESTROY_RINGS);
+                               /* there might be handshake issue with hardware which needs delay */
+                               mdelay(20);
+                               /* Wait for response flag (bit 31) */
+                               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
+                                               0x80000000, 0x80000000, false);
+               }
        }
 
        return ret;
@@ -118,14 +142,44 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp,
                                   0x80000000, 0x8000FFFF, false);
 
        } else {
-               /* Wait for sOS ready for ring creation */
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
-                                  0x80000000, 0x80000000, false);
+               if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) {
+                       /* Wait for sOS ready for ring creation */
+                       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64),
+                                       0x80000000, 0x80000000, false);
                if (ret) {
                        DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
                        return ret;
                }
 
+               /* Write low address of the ring to C2PMSG_69 */
+               psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+               WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_69, psp_ring_reg);
+               /* Write high address of the ring to C2PMSG_70 */
+               psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+               WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_70, psp_ring_reg);
+               /* Write size of ring to C2PMSG_71 */
+               psp_ring_reg = ring->ring_size;
+               WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_71, psp_ring_reg);
+               /* Write the ring initialization command to C2PMSG_64 */
+               psp_ring_reg = ring_type;
+               psp_ring_reg = psp_ring_reg << 16;
+               WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64, psp_ring_reg);
+
+               /* there might be handshake issue with hardware which needs delay */
+               mdelay(20);
+
+               /* Wait for response flag (bit 31) in C2PMSG_64 */
+               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_64),
+                                  0x80000000, 0x8000FFFF, false);
+               } else {
+                       /* Wait for sOS ready for ring creation */
+                       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
+                                          0x80000000, 0x80000000, false);
+                       if (ret) {
+                               DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
+                               return ret;
+                       }
+
                /* Write low address of the ring to C2PMSG_69 */
                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
                WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg);
@@ -146,6 +200,7 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
                                   0x80000000, 0x8000FFFF, false);
+               }
        }
 
        return ret;
@@ -176,8 +231,12 @@ static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp)
 
        if (amdgpu_sriov_vf(adev))
                data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
-       else
-               data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
+       else {
+               if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5))
+                       data = RREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_67);
+               else
+                       data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
+               }
 
        return data;
 }
@@ -190,8 +249,12 @@ static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
                WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
                WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
                             GFX_CTRL_CMD_ID_CONSUME_CMD);
-       } else
-               WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
+       } else {
+               if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5))
+                       WREG32_SOC15(MP0, 0, regMPASP_PCRU0_MPASP_C2PMSG_67, value);
+               else
+                       WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
+       }
 }
 
 static const struct psp_funcs psp_v15_0_0_funcs = {