+2025-08-31 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+
+ * config/xtensa/predicates.md (alt_ubranch_operator):
+ New predicate.
+ * config/xtensa/xtensa.md (*eqne_in_range):
+ New insn_and_split pattern.
+
+2025-08-31 Shreya Munnangi <smunnangi1@ventanamicro.com>
+
+ * config/riscv/riscv-protos.h (synthesize_add_extended): Prototype.
+ * config/riscv/riscv.cc (synthesize_add_extended): New function.
+ * config/riscv/riscv.md (addsi3): For RV64, try synthesize_add_extended.
+
+2025-08-31 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/install.texi (Binaries): Drop MinGW.
+
2025-08-30 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121698
+2025-08-31 Paul Thomas <pault@gcc.gnu.org>
+
+ PR fortran/99709
+ * trans-array.cc (structure_alloc_comps): For the case
+ COPY_ALLOC_COMP, do a deep copy of non-allocatable PDT arrays
+ Suppress the use of 'duplicate_allocatable' for PDT arrays.
+ * trans-expr.cc (conv_dummy_value): When passing to a PDT dummy
+ with the VALUE attribute, do a deep copy to ensure that
+ parameterized components are reallocated.
+
2025-08-29 Harald Anlauf <anlauf@gmx.de>
PR fortran/93330
+2025-08-31 Paul Thomas <pault@gcc.gnu.org>
+
+ PR fortran/99709
+ * gfortran.dg/pdt_41.f03: New test.
+
+2025-08-31 Shreya Munnangi <smunnangi1@ventanamicro.com>
+
+ * gcc.target/riscv/add-synthesis-2.c: New test.
+
+2025-08-31 Pan Li <pan2.li@intel.com>
+
+ * gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c: New test.
+ * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c: New test.
+
2025-08-30 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121698
+2025-08-31 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/xml/manual/using_exceptions.xml: Update link to
+ Boost's "Exception-Safety"
+ * doc/html/manual/using_exceptions.html: Rebuild.
+
+2025-08-31 Jonathan Wakely <jwakely@redhat.com>
+
+ * src/c++26/debugging.cc [_GLIBCXX_HAVE_SYS_PTRACE_H]: Include
+ <sys/types.h>.
+ (breakpoint) [__i386__ || __x86_64__]: Use "int 0x03" instead of
+ "int3".
+
2025-08-28 Jonathan Wakely <jwakely@redhat.com>
PR libstdc++/119670