crypto: qat - add adf_rl_get_num_svc_aes() in rate limiting

Enhance the rate limiting (RL) infrastructure by adding
adf_rl_get_num_svc_aes() which can be used to fetch the number of engines
associated with the service type. Expand the structure adf_rl_hw_data
with an array that contains the number of AEs per service.

Implement adf_gen4_init_num_svc_aes() for QAT GEN4 devices to calculate
the total number of acceleration engines dedicated to a specific service.

Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
index 32bb9e1826d2022d49403c5901332ccad32cb9fb..67a1c1d8e23ea2db31180f6e39579bc9224f4b0b 100644 (file)
--- a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
@@ -301,6 +301,8 @@ static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)
        rl_data->max_tp[SVC_DC] = ADF_420XX_RL_MAX_TP_DC;
        rl_data->scan_interval = ADF_420XX_RL_SCANS_PER_SEC;
        rl_data->scale_ref = ADF_420XX_RL_SLICE_REF;
+
+       adf_gen4_init_num_svc_aes(rl_data);
 }
 
 static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)

diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
index f917cc9db09d515f92a4228cf82fe886d42a67de..9b728dba048b56f6de7972d2114c096677cd3796 100644 (file)
--- a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -227,6 +227,8 @@ static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)
        rl_data->max_tp[SVC_DC] = ADF_4XXX_RL_MAX_TP_DC;
        rl_data->scan_interval = ADF_4XXX_RL_SCANS_PER_SEC;
        rl_data->scale_ref = ADF_4XXX_RL_SLICE_REF;
+
+       adf_gen4_init_num_svc_aes(rl_data);
 }
 
 static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
index 3103755e416e720f48f3be11a5bd3a78d7495dda..5e4b45c3fabefe52471ec2948a20c617143cbe79 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
@@ -558,3 +558,25 @@ void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
        dc_ops->build_decomp_block = adf_gen4_build_decomp_block;
 }
 EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);
+
+void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data)
+{
+       struct adf_hw_device_data *hw_data;
+       unsigned int i;
+       u32 ae_cnt;
+
+       hw_data = container_of(device_data, struct adf_hw_device_data, rl_data);
+       ae_cnt = hweight32(hw_data->get_ae_mask(hw_data));
+       if (!ae_cnt)
+               return;
+
+       for (i = 0; i < SVC_BASE_COUNT; i++)
+               device_data->svc_ae_mask[i] = ae_cnt - 1;
+
+       /*
+        * The decompression service is not supported on QAT GEN4 devices.
+        * Therefore, set svc_ae_mask to 0.
+        */
+       device_data->svc_ae_mask[SVC_DECOMP] = 0;
+}
+EXPORT_SYMBOL_GPL(adf_gen4_init_num_svc_aes);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
index 7f2b9cb0fe609ccc739bfa576bb3040eaf3fb817..7fa203071c012752790432acdb0762156ad41dc4 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
@@ -175,5 +175,6 @@ void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev,
                                u32 bank_number);
 bool adf_gen4_services_supported(unsigned long service_mask);
 void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
+void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data);
 
 #endif

diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.c b/drivers/crypto/intel/qat/qat_common/adf_rl.c
index 92697553974093dd38d7cb78279365c0bf9f0fe8..77465ab6702c3c10b1f20940266c1bc266739028 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_rl.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_rl.c
@@ -552,6 +552,17 @@ u32 adf_rl_calculate_slice_tokens(struct adf_accel_dev *accel_dev, u32 sla_val,
        return allocated_tokens;
 }
 
+static u32 adf_rl_get_num_svc_aes(struct adf_accel_dev *accel_dev,
+                                 enum adf_base_services svc)
+{
+       struct adf_rl_hw_data *device_data = &accel_dev->hw_device->rl_data;
+
+       if (svc >= SVC_BASE_COUNT)
+               return 0;
+
+       return device_data->svc_ae_mask[svc];
+}
+
 u32 adf_rl_calculate_ae_cycles(struct adf_accel_dev *accel_dev, u32 sla_val,
                               enum adf_base_services svc_type)
 {
@@ -563,7 +574,7 @@ u32 adf_rl_calculate_ae_cycles(struct adf_accel_dev *accel_dev, u32 sla_val,
                return 0;
 
        avail_ae_cycles = hw_data->clock_frequency;
-       avail_ae_cycles *= hw_data->get_num_aes(hw_data) - 1;
+       avail_ae_cycles *= adf_rl_get_num_svc_aes(accel_dev, svc_type);
        do_div(avail_ae_cycles, device_data->scan_interval);
 
        sla_val *= device_data->max_tp[svc_type];

diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.h b/drivers/crypto/intel/qat/qat_common/adf_rl.h
index dee7f0c81906063e6f46348f61def5704caa0ce7..59f88591615772f52cb0a92982c14032be116092 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_rl.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_rl.h
@@ -89,6 +89,7 @@ struct adf_rl_hw_data {
        u32 pcie_scale_div;
        u32 dcpr_correction;
        u32 max_tp[RL_ROOT_MAX];
+       u32 svc_ae_mask[SVC_BASE_COUNT];
        struct rl_slice_cnt slices;
 };