Revert "RISC-V: Add basic support for the Ventana-VT1 core"

This reverts commit b4fca4fc70dc76cf18406fd2b046c834d976aa90.

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24ea4152115c940e2430d69e415ac22..31ad34682c548c823a706f5cbd55033415392e0d 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -38,7 +38,6 @@ RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
 RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
 RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
-RISCV_TUNE("ventana-vt1", generic, ventana_vt1_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
 
 #undef RISCV_TUNE
@@ -74,6 +73,4 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",   "ventana-vt1")
-
 #undef RISCV_CORE

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1be83b5107c6df24f1428d6654359ce5aa7b7e27..25fd85b09b1e3257960d292251a70ee468fb6d9e 100644 (file)
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -52,7 +52,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
 /* Keep this list in sync with define_attr "tune" in riscv.md.  */
 enum riscv_microarchitecture_type {
   generic,
-  sifive_7,
+  sifive_7
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
 

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index cceddd7053387e78dea13f77cf32be79162a655c..e36ff05695a6a27d2ae803d5007f0fe36acbdc3c 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -360,20 +360,6 @@ static const struct riscv_tune_param optimize_size_tune_info = {
   false,                                       /* slow_unaligned_access */
 };
 
-/* Costs to use when optimizing for Ventana Micro VT1.  */
-static const struct riscv_tune_param ventana_vt1_tune_info = {
-  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},      /* fp_add */
-  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},      /* fp_mul */
-  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},    /* fp_div */
-  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},      /* int_mul */
-  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},      /* int_div */
-  4,                                           /* issue_rate */
-  4,                                           /* branch_cost */
-  5,                                           /* memory_cost */
-  8,                                           /* fmv_cost */
-  false,                                       /* slow_unaligned_access */
-};
-
 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dc2da464ebb06c35c87a8f7b10d16edb8717328b..40f667a630ad6af31acbbc3a873a04dbecacac16 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -28770,15 +28770,14 @@ by particular CPU name.
 Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
 @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
 @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
-@samp{sifive-u54}, @samp{sifive-u74}, and @samp{ventana-vt1}.
+@samp{sifive-u54}, and @samp{sifive-u74}.
 
 @item -mtune=@var{processor-string}
 @opindex mtune
 Optimize the output for the given processor, specified by microarchitecture or
 particular CPU name.  Permissible values for this option are: @samp{rocket},
 @samp{sifive-3-series}, @samp{sifive-5-series}, @samp{sifive-7-series},
-@samp{thead-c906}, @samp{ventana-vt1}, @samp{size}, and all valid options for
-@option{-mcpu=}.
+@samp{thead-c906}, @samp{size}, and all valid options for @option{-mcpu=}.
 
 When @option{-mtune=} is not specified, use the setting from @option{-mcpu},
 the default is @samp{rocket} if both are not specified.