int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct net_device *dev, enum tc_setup_type type,
void *type_data);
+int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex,
+ u32 direction, u32 i_count_addr,
+ u32 o_status_addr, u32 o_count_addr);
#else
static inline void mt76_npu_check_ppe(struct mt76_dev *dev,
struct sk_buff *skb, u32 info)
{
return -EOPNOTSUPP;
}
+
+static inline int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex,
+ u32 direction, u32 i_count_addr,
+ u32 o_status_addr, u32 o_count_addr)
+{
+ return -EOPNOTSUPP;
+}
#endif /* CONFIG_MT76_NPU */
static inline bool mt76_npu_device_active(struct mt76_dev *dev)
addr++;
}
+ if (is_mt7996(&dev->mt76) &&
+ mt76_npu_device_active(&dev->mt76))
+ mt76_npu_send_txrx_addr(&dev->mt76, 0, i,
+ dev->wed_rro.addr_elem[i].phy_addr,
+ 0, 0);
+
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) {
addr++;
}
+ if (is_mt7996(&dev->mt76) && mt76_npu_device_active(&dev->mt76))
+ mt76_npu_send_txrx_addr(&dev->mt76, 1, 0,
+ dev->wed_rro.session.phy_addr, 0, 0);
+
mt7996_rro_hw_init(dev);
return mt7996_dma_rro_init(dev);
list);
list_del_init(&e->list);
- if (mt76_npu_device_active(&dev->mt76))
+ if (mt76_npu_device_active(&dev->mt76)) {
+ if (is_mt7996(&dev->mt76))
+ mt76_npu_send_txrx_addr(&dev->mt76, 3, e->id,
+ 0, 0, 0);
goto reset_session;
+ }
for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
void *ptr = dev->wed_rro.session.ptr;
}
EXPORT_SYMBOL_GPL(mt76_npu_net_setup_tc);
+int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex,
+ u32 direction, u32 i_count_addr,
+ u32 o_status_addr, u32 o_count_addr)
+{
+ struct {
+ __le32 dir;
+ __le32 in_count_addr;
+ __le32 out_status_addr;
+ __le32 out_count_addr;
+ } info = {
+ .dir = cpu_to_le32(direction),
+ .in_count_addr = cpu_to_le32(i_count_addr),
+ .out_status_addr = cpu_to_le32(o_status_addr),
+ .out_count_addr = cpu_to_le32(o_count_addr),
+ };
+ struct airoha_npu *npu;
+ int err = -ENODEV;
+
+ rcu_read_lock();
+ npu = rcu_dereference(dev->mmio.npu);
+ if (npu)
+ err = airoha_npu_wlan_send_msg(npu, ifindex,
+ WLAN_FUNC_SET_WAIT_INODE_TXRX_REG_ADDR,
+ &info, sizeof(info), GFP_ATOMIC);
+ rcu_read_unlock();
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(mt76_npu_send_txrx_addr);
+
void mt76_npu_disable_irqs(struct mt76_dev *dev)
{
struct airoha_npu *npu;