arm64: dts: qcom: x1e80100: Fix PHY for DP2

[ Upstream commit ba728bda663b0e812cb20450d18af5d0edd803a2 ]

The actual PHY used by MDSS DP2 is the USB SS2 QMP one. So switch to it
instead. This is needed to get external DP support on boards like CRD
where the 3rd Type-C USB port (right-hand side) is connected to DP2.

Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240829-x1e80100-dts-dp2-use-qmpphy-ss2-v1-1-9ba3dca61ccc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 36c398e5fe5016649fbd0bf88f3fc6ce26faa46f..64d5f6e4c0b01819042bbf449ca71e75ed4c7457 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3998,14 +3998,14 @@
 
                                assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
                                                  <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss_dp2_phy 0>,
-                                                        <&mdss_dp2_phy 1>;
+                               assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                operating-points-v2 = <&mdss_dp2_opp_table>;
 
                                power-domains = <&rpmhpd RPMHPD_MMCX>;
 
-                               phys = <&mdss_dp2_phy>;
+                               phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
                                phy-names = "dp";
 
                                #sound-dai-cells = <0>;
@@ -4189,8 +4189,8 @@
                                 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
                                 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
                                 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
-                                <&mdss_dp2_phy 0>, /* dp2 */
-                                <&mdss_dp2_phy 1>,
+                                <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
+                                <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
                                 <&mdss_dp3_phy 0>, /* dp3 */
                                 <&mdss_dp3_phy 1>;
                        power-domains = <&rpmhpd RPMHPD_MMCX>;